component
GP7574D
Public Made by Adomby adom
HaloChip Power Distribution Switches, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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GP7574D
HaloChip · Power Distribution Switches · SOP-8
GP7574D from HaloChip, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Chip ground pin; one of three GND pins on the SOP8 package. |
| 2 | GND | power_in | Chip ground pin; one of three GND pins on the SOP8 package. |
| 3 | GND | power_in | Chip ground pin; one of three GND pins on the SOP8 package. |
| 4 | VCC | power_in | Chip power supply pin, to be bypassed by a capacitor placed close to it; recommended VCC operating voltage is 5 V and the absolute maximum is 6 V, with UVLO turn-on at 2.8 V and turn-off at 3.7 V. |
| 5 | SW | passive | Drain of the internal power MOSFET; for the GP7574D the SW working voltage is limited to 40 V (recommended 4.7 to 36 V, with 10% derating). |
| 6 | SW | passive | Drain of the internal power MOSFET; for the GP7574D the SW working voltage is limited to 40 V (recommended 4.7 to 36 V, with 10% derating). |
| 7 | SW | passive | Drain of the internal power MOSFET; for the GP7574D the SW working voltage is limited to 40 V (recommended 4.7 to 36 V, with 10% derating). |
| 8 | SW | passive | Drain of the internal power MOSFET; for the GP7574D the SW working voltage is limited to 40 V (recommended 4.7 to 36 V, with 10% derating). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | HaloChip |
| Package | SOP-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
GP7574D - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
gp7574d-etched.step/gp7574d-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);gp7574d.step/gp7574d.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: HaloChip datasheet (7 pp, sha256
a6b44523477fa0e5, retrieved 2026-10-10, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# GP7574D
**HaloChip** · Power Distribution Switches · SOP-8
GP7574D from HaloChip, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Chip ground pin; one of three GND pins on the SOP8 package. |
| 2 | GND | power_in | Chip ground pin; one of three GND pins on the SOP8 package. |
| 3 | GND | power_in | Chip ground pin; one of three GND pins on the SOP8 package. |
| 4 | VCC | power_in | Chip power supply pin, to be bypassed by a capacitor placed close to it; recommended VCC operating voltage is 5 V and the absolute maximum is 6 V, with UVLO turn-on at 2.8 V and turn-off at 3.7 V. |
| 5 | SW | passive | Drain of the internal power MOSFET; for the GP7574D the SW working voltage is limited to 40 V (recommended 4.7 to 36 V, with 10% derating). |
| 6 | SW | passive | Drain of the internal power MOSFET; for the GP7574D the SW working voltage is limited to 40 V (recommended 4.7 to 36 V, with 10% derating). |
| 7 | SW | passive | Drain of the internal power MOSFET; for the GP7574D the SW working voltage is limited to 40 V (recommended 4.7 to 36 V, with 10% derating). |
| 8 | SW | passive | Drain of the internal power MOSFET; for the GP7574D the SW working voltage is limited to 40 V (recommended 4.7 to 36 V, with 10% derating). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | HaloChip |
| Package | SOP-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
## CAD (KiCad official)
- Symbol: `GP7574D`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `gp7574d-etched.step` / `gp7574d-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `gp7574d.step` / `gp7574d.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [HaloChip datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8600519938649956352) (7 pp, sha256 `a6b44523477fa0e5`, retrieved 2026-10-10, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/gp7574d-datasheet.pdf)