main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 1mo ago
viewers gp7574d: viewers · Ray 1mo ago
gp7574d-etched.glb gp7574d: factory component page (tier=lcsc) · Ray 1mo ago
gp7574d-etched.step gp7574d: factory component page (tier=lcsc) · Ray 1mo ago
gp7574d-hero.glb gp7574d: hero GLB from the etched model (keeps the MPN mark) · Ray 1mo ago
gp7574d-hero.overlay.json Publish 0.1.0 · Ray 1mo ago
gp7574d.glb Publish 0.1.0 · Ray 1mo ago
gp7574d.kicad_mod Publish 0.1.0 · Ray 1mo ago
gp7574d.kicad_sym Publish 0.1.0 · Ray 1mo ago
gp7574d.lbr Publish 0.1.0 · Ray 1mo ago
gp7574d.step Publish 0.1.0 · Ray 1mo ago
package.json Publish 0.1.0 · Ray 1mo ago
page.json Set visibility: public · Ray 1mo ago
README.md Publish 0.1.0 · Ray 1mo ago

GP7574D

HaloChip · Power Distribution Switches · SOP-8

GP7574D from HaloChip, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Chip ground pin; one of three GND pins on the SOP8 package.
2 GND power_in Chip ground pin; one of three GND pins on the SOP8 package.
3 GND power_in Chip ground pin; one of three GND pins on the SOP8 package.
4 VCC power_in Chip power supply pin, to be bypassed by a capacitor placed close to it; recommended VCC operating voltage is 5 V and the absolute maximum is 6 V, with UVLO turn-on at 2.8 V and turn-off at 3.7 V.
5 SW passive Drain of the internal power MOSFET; for the GP7574D the SW working voltage is limited to 40 V (recommended 4.7 to 36 V, with 10% derating).
6 SW passive Drain of the internal power MOSFET; for the GP7574D the SW working voltage is limited to 40 V (recommended 4.7 to 36 V, with 10% derating).
7 SW passive Drain of the internal power MOSFET; for the GP7574D the SW working voltage is limited to 40 V (recommended 4.7 to 36 V, with 10% derating).
8 SW passive Drain of the internal power MOSFET; for the GP7574D the SW working voltage is limited to 40 V (recommended 4.7 to 36 V, with 10% derating).

Key specifications

Parameter Value
Manufacturer HaloChip
Package SOP-8
Category Power Management (PMIC)
Pins 8

CAD (KiCad official)

  • Symbol: GP7574D
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: gp7574d-etched.step / gp7574d-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); gp7574d.step / gp7574d.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HaloChip datasheet (7 pp, sha256 a6b44523477fa0e5, retrieved 2026-10-10, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF