GN74HC595D

{
  "slug": "gn74hc595d",
  "version": "0.1.0",
  "type": "component",
  "description": "GN Semic Shift Registers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "logic",
    "gn74hc595d",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
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  "files": [
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    "README.md",
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    "gn74hc595d.glb",
    "gn74hc595d.step",
    "gn74hc595d.lbr",
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    "docs/gn74hc595d-datasheet.pdf",
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    "viewers/footprint.html",
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    "gn74hc595d-hero.overlay.json",
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  "component": {
    "mpn": "GN74HC595D",
    "manufacturer": "GN Semic",
    "package": "SOP-16",
    "pin_count": 16,
    "category": "Logic",
    "subcategory": "Shift Registers",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603385994418794496",
    "parts": {
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      "footprint": "gn74hc595d.kicad_mod",
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      "lbr": "gn74hc595d.lbr"
    },
    "distributor_links": {
      "lcsc": "C22461436"
    },
    "distributor_check": {
      "checked_at": "2026-10-19T02:18:45Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "no match"
      },
      "mouser": {
        "pn": null,
        "status": "no match"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "Q1",
        "type": "tri_state",
        "description": "Three-state parallel output bit Q1 of the 8-bit storage register; outputs Q0-Q7 go to high impedance when G is high."
      },
      {
        "number": "2",
        "name": "Q2",
        "type": "tri_state",
        "description": "Three-state parallel output bit Q2 of the 8-bit storage register; outputs Q0-Q7 go to high impedance when G is high."
      },
      {
        "number": "3",
        "name": "Q3",
        "type": "tri_state",
        "description": "Three-state parallel output bit Q3 of the 8-bit storage register; outputs Q0-Q7 go to high impedance when G is high."
      },
      {
        "number": "4",
        "name": "Q4",
        "type": "tri_state",
        "description": "Three-state parallel output bit Q4 of the 8-bit storage register; outputs Q0-Q7 go to high impedance when G is high."
      },
      {
        "number": "5",
        "name": "Q5",
        "type": "tri_state",
        "description": "Three-state parallel output bit Q5 of the 8-bit storage register; outputs Q0-Q7 go to high impedance when G is high."
      },
      {
        "number": "6",
        "name": "Q6",
        "type": "tri_state",
        "description": "Three-state parallel output bit Q6 of the 8-bit storage register; outputs Q0-Q7 go to high impedance when G is high."
      },
      {
        "number": "7",
        "name": "Q7",
        "type": "tri_state",
        "description": "Three-state parallel output bit Q7 of the 8-bit storage register; outputs Q0-Q7 go to high impedance when G is high."
      },
      {
        "number": "8",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference (0 V) for the device."
      },
      {
        "number": "9",
        "name": "Q7'",
        "type": "output",
        "description": "Serial data output of the shift register, used for cascading devices; it is cleared to 0 by SCLR low."
      },
      {
        "number": "10",
        "name": "SCLR",
        "type": "input",
        "description": "Active-low shift register clear; when low, the shift register is cleared (Q7' = 0) and the storage state is not affected."
      },
      {
        "number": "11",
        "name": "SCK",
        "type": "input",
        "description": "Shift register clock for serial data input; data shifts on the rising edge, with shift clock frequency rated DC to 30 MHz."
      },
      {
        "number": "12",
        "name": "RCK",
        "type": "input",
        "description": "Storage (output latch) register clock; a rising edge latches the shift register contents into the output register."
      },
      {
        "number": "13",
        "name": "G",
        "type": "input",
        "description": "Output enable, active low; when G is low the Q0-Q7 outputs are enabled, and when G is high they are forced to high impedance."
      },
      {
        "number": "14",
        "name": "SER",
        "type": "input",
        "description": "Serial data input to the 8-bit shift register (feeds Q0); setup and hold times to SCK are specified in the AC characteristics."
      },
      {
        "number": "15",
        "name": "Q0",
        "type": "tri_state",
        "description": "Three-state parallel output bit Q0 of the 8-bit storage register; outputs Q0-Q7 go to high impedance when G is high."
      },
      {
        "number": "16",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply; recommended operating range 2 V to 6 V, absolute maximum -0.5 V to 7.0 V."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The pin table on page 2 lists 16 pins and the package list on page 1 gives SOP16 for GN74HC595D, so ; Pin types for Q0-Q7 are marked tri_state based on the datasheet's 'three-state output' label; the da; Datasheet pin names carry no overbar in the extracted text; SCLR and G are treated as active-low per",
          "1/16 pin names appear NOWHERE in the datasheet text: [\"9:Q7'@p2\"]"
        ],
        "pages_sent": 13,
        "cost_usd": 0.0545,
        "at": "2026-10-19T02:16:21"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603385994418794496",
        "pages": 13,
        "sha256": "04891aced7a7e2c2",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
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        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          9.9,
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        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
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        "checked": "2026-10-19",
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        "zmin_mm": -0.0,
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        "sha256": "50d2641daf7c2a9ffd8003d18c28db3a71efebc9db3cd0431bb61e82f4e9b420",
        "checked": "2026-10-19",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
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  }
}