Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

GN74HC595D

GN Semic · Shift Registers · SOP-16

GN74HC595D from GN Semic, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q1 tri_state Three-state parallel output bit Q1 of the 8-bit storage register; outputs Q0-Q7 go to high impedance when G is high.
2 Q2 tri_state Three-state parallel output bit Q2 of the 8-bit storage register; outputs Q0-Q7 go to high impedance when G is high.
3 Q3 tri_state Three-state parallel output bit Q3 of the 8-bit storage register; outputs Q0-Q7 go to high impedance when G is high.
4 Q4 tri_state Three-state parallel output bit Q4 of the 8-bit storage register; outputs Q0-Q7 go to high impedance when G is high.
5 Q5 tri_state Three-state parallel output bit Q5 of the 8-bit storage register; outputs Q0-Q7 go to high impedance when G is high.
6 Q6 tri_state Three-state parallel output bit Q6 of the 8-bit storage register; outputs Q0-Q7 go to high impedance when G is high.
7 Q7 tri_state Three-state parallel output bit Q7 of the 8-bit storage register; outputs Q0-Q7 go to high impedance when G is high.
8 GND power_in Ground reference (0 V) for the device.
9 Q7' output Serial data output of the shift register, used for cascading devices; it is cleared to 0 by SCLR low.
10 SCLR input Active-low shift register clear; when low, the shift register is cleared (Q7' = 0) and the storage state is not affected.
11 SCK input Shift register clock for serial data input; data shifts on the rising edge, with shift clock frequency rated DC to 30 MHz.
12 RCK input Storage (output latch) register clock; a rising edge latches the shift register contents into the output register.
13 G input Output enable, active low; when G is low the Q0-Q7 outputs are enabled, and when G is high they are forced to high impedance.
14 SER input Serial data input to the 8-bit shift register (feeds Q0); setup and hold times to SCK are specified in the AC characteristics.
15 Q0 tri_state Three-state parallel output bit Q0 of the 8-bit storage register; outputs Q0-Q7 go to high impedance when G is high.
16 VCC power_in Positive supply; recommended operating range 2 V to 6 V, absolute maximum -0.5 V to 7.0 V.

Key specifications

Parameter Value
Manufacturer GN Semic
Package SOP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 7 V 3
Supply current ICC -70 70 mA 3
DC input voltage VIN -1.5 V rated range printed as -1.5~VCC+1.5 3
DC output voltage VOUT -0.5 V rated range printed as -0.5~VCC+0.5 3
Clamp diode current IIK,IOK -20 20 mA 3
DC output current IOUT -35 35 mA 3
Power dissipation PD (SOP package) PD 500 mW SOP package 3
Operating ambient temperature Tamb -40 85 ℃ 3
Storage temperature Tstg -65 150 ℃ 3
Soldering temperature TL (SOP package) TL 250 ℃ SOP package 3
Supply voltage VCC 2 6 V 3
DC input or output voltage VIN 或 VOUT 0 V upper limit printed as VCC 3
Input rise and fall time tr,tf 1000 ns VCC=2.0V 3
Input rise and fall time tr,tf 500 ns VCC=4.5V 3
Input rise and fall time tr,tf 400 ns VCC=6.0V 3
Quiescent supply current ICCQ 80 uA VIN=VCC or GND, VCC=6.0V, IOUT=0uA; Tamb=-40~85℃ 4
Three-state output leakage current IOZ -5 5 uA VIN=VIH or VIL, VOUT=VCC or GND, VCC=6.0V 4
Input current IIN -1 1 uA VIN=VCC or GND, VCC=6.0V 4
High-level input voltage VIH 1.5 V VCC=2.0V 4
High-level input voltage VIH 3.15 V VCC=4.5V 4
High-level input voltage VIH 4.2 V VCC=6.0V 4
Low-level input voltage VIL 0.5 V VCC=2.0V 4
Low-level input voltage VIL 1.35 V VCC=4.5V 4
Low-level input voltage VIL 1.8 V VCC=6.0V 4
High-level output voltage VOH 1.9 V IOUT=-20uA, VCC=2.0V 4
High-level output voltage VOH 4.4 V IOUT=-20uA, VCC=4.5V 4
High-level output voltage VOH 5.9 V IOUT=-20uA, VCC=6.0V 4
High-level output voltage Q7' VOH 3.7 V IOUT=-4.0mA, VCC=4.5V 4
High-level output voltage Q7' VOH 5.2 V IOUT=-5.2mA, VCC=6.0V 4
High-level output voltage Q0-Q7 VOH 3.7 V IOUT=-6.0mA, VCC=4.5V 4
High-level output voltage Q0-Q7 VOH 5.2 V IOUT=-7.8mA, VCC=6.0V 4
Low-level output voltage VOL 0.1 V IOUT=20uA, VCC=2.0V 4
Low-level output voltage Q7' VOL 0.33 V IOUT=4.0mA, VCC=4.5V 4
Low-level output voltage Q0-Q7 VOL 0.33 V IOUT=6.0mA, VCC=4.5V 4
SCK/RCK maximum clock frequency fMAX 9 MHz TA=25℃, tr=tf=6ns, CL=50pF, VCC=2.0V 5
SCK/RCK maximum clock frequency fMAX 30 MHz TA=25℃, tr=tf=6ns, CL=50pF, VCC=4.5V 5
SCK/RCK maximum clock frequency fMAX 35 MHz TA=25℃, tr=tf=6ns, CL=50pF, VCC=6.0V 5

CAD (KiCad official)

  • Symbol: GN74HC595D
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: gn74hc595d-etched.step / gn74hc595d-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); gn74hc595d.step / gn74hc595d.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: GN Semic datasheet (13 pp, sha256 04891aced7a7e2c2, retrieved 2026-10-19, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF