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GBI5132QYAR

GOSEMICON · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · QFN-20-EP(3.5x3.5)

GBI5132QYAR from GOSEMICON, in a QFN-20-EP(3.5x3.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT power_out Regulated output pin; a 22µF or larger capacitor (10µF or greater effective capacitance) is required for stability and should be placed as close to the device as possible.
2 SNS input Output voltage sense pin, connected only when setting OUT by PCB layout with no external resistor; keep floating when OUT is set by an external resistor divider.
3 FB input Feedback pin to the error amplifier; a 10nF feed-forward capacitor between FB and OUT is recommended, though it may disrupt Power-Good (PG) functionality.
4 PG output Open-drain power-good output that is active high when the output is above 91% of target and pulled low below 85% of target, during EN shutdown, OTP, or OCP.
5 25mV input Voltage-setting pin for the internal feedback network; connect to GND or SNS to select the output voltage, or leave floating when not in use.
6 50mV input Voltage-setting pin for the internal feedback network; connect to GND or SNS to select the output voltage, or leave floating when not in use.
7 100mV input Voltage-setting pin for the internal feedback network; connect to GND or SNS to select the output voltage, or leave floating when not in use.
8 GND power_in Ground pin that must be connected to ground, the thermal pad, and the other GND pins with a low-impedance connection.
9 200mV input Voltage-setting pin for the internal feedback network; connect to GND or SNS to select the output voltage, or leave floating when not in use.
10 400mV input Voltage-setting pin for the internal feedback network; connect to GND or SNS to select the output voltage, or leave floating when not in use.
11 800mV input Voltage-setting pin for the internal feedback network; connect to GND or SNS to select the output voltage, or leave floating when not in use.
12 BIAS input BIAS supply pin that enables low-input, low-output (LILO) operation; a 1µF capacitor (0.47µF or larger) must be connected to ground, and the pin may be left floating or tied to ground if unused.
13 NR/SS bidirectional Noise-reduction and soft-start pin; an external capacitor to ground reduces reference noise and enables soft-start, with 10nF or larger recommended as close to the pin as possible.
14 EN input Enable pin; logic high enables the device and logic low disables it, and it must be tied to IN or BIAS if enable functionality is not required.
15 IN power_in Input supply voltage pin; a 10µF or larger ceramic capacitor (5µF or greater effective) from IN to ground is required, placed as close as possible to the input.
16 IN power_in Input supply voltage pin; a 10µF or larger ceramic capacitor (5µF or greater effective) from IN to ground is required, placed as close as possible to the input.
17 IN power_in Input supply voltage pin; a 10µF or larger ceramic capacitor (5µF or greater effective) from IN to ground is required, placed as close as possible to the input.
18 GND power_in Ground pin that must be connected to ground, the thermal pad, and the other GND pins with a low-impedance connection.
19 OUT power_out Regulated output pin; a 22µF or larger capacitor (10µF or greater effective capacitance) is required for stability and should be placed as close to the device as possible.
20 OUT power_out Regulated output pin; a 22µF or larger capacitor (10µF or greater effective capacitance) is required for stability and should be placed as close to the device as possible.
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer GOSEMICON
Package QFN-20-EP(3.5x3.5)
Category Power Management (PMIC)
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Voltage: IN, BIAS, PG, EN -0.3 7 V 4
Voltage: SNS, OUT (printed max IN+0.3 V, not numeric) -0.3 V 4
Voltage: NR/SS, FB -0.3 3.6 V 4
Voltage: 25mV, 50mV, 100mV, 200mV, 400mV, 800mV pins (printed max OUT+0.3 V, not numeric) -0.3 V 4
Current: PG 5 mA 4
Operating junction temperature TJ -40 125 °C 4
Storage temperature TSTG -65 150 °C 4
Input supply voltage range VIN 1.1 6.5 V 4
Bias supply voltage range VBIAS 3 6.5 V 4
Output voltage range VOUT 0.5 5.15 V 4
Enable voltage range (printed max is VIN, not numeric) VEN 0 V 4
Output current IOUT 0 3 A 4
Input capacitor CIN 10 47 μF 4
Output capacitor COUT 47 100 μF 5
Power-good pullup resistance RPG 10 100 kΩ 5
Operating junction temperature TJ -40 125 ℃ 5
Input supply voltage range VIN 1.1 6.5 V 5
Input supply voltage range (bias) VBIAS 3 6.5 V VIN = 1.1V 5
Dropout voltage VDO 60 120 mV VIN = 1.4V, IOUT = 3A, VFB = 0.5V -3% 6
Output voltage range VOUT 0.5 2.075 V Using programming pin 6
Output voltage range VOUT 0.5 5.15 V Using external resistors 6
Output voltage accuracy VOUT -1 1 % 0.5V ≤ VOUT ≤ 5.15V, 5mA ≤ IOUT ≤ 3A, over VIN, -40~85℃ 6
Output voltage accuracy VOUT -1.5 1.5 % 0.5V ≤ VOUT ≤ 5.15V, 5mA ≤ IOUT ≤ 3A, over VIN, -40~125℃ 6
Output voltage accuracy with BIAS VOUT -1 1 % 0.5V ≤ VOUT ≤ 5.15V, 5mA ≤ IOUT ≤ 3A, 3V ≤ VBIAS ≤ 6.5V, -40~85℃ 6
Output voltage accuracy with BIAS VOUT -1.5 1.5 % 0.5V ≤ VOUT ≤ 5.15V, 5mA ≤ IOUT ≤ 3A, 3V ≤ VBIAS ≤ 6.5V, -40~125℃ 6
NR/SS pin charging current INR/SS 4.5 6 7.5 μA VNR/SS = 0V, VIN = 6.5V 6
FB pin leakage current IFB -100 100 nA VIN = 6.5V 6
PG pin threshold VPG_IT 80 85 90 % For falling VOUT 8
Junction-to-ambient thermal resistance (single printed value, QFN20 column) RθJA 43 °C/W 5
Junction-to-case (top) thermal resistance (single printed value, QFN20 column) RθJC(top) 38 °C/W 5
Junction-to-top characterization parameter (single printed value, QFN20 column) ψJT 0.8 °C/W 5
Junction-to-board characterization parameter (single printed value, QFN20 column) ψJB 17.5 °C/W 5

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper - Place ground return connections to the input and output capacitor, and to the LDO ground pin as close as possible to each other, connected by a wide, component-side, copper surface. 31

CAD (KiCad official)

  • Symbol: GBI5132QYAR
  • Footprint: Package_DFN_QFN:QFN-20-1EP_3.5x3.5mm_P0.5mm_EP2x2mm
  • 3D model: QFN-20-EP(3.5x3.5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: gbi5132qyar-etched.step / gbi5132qyar-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); gbi5132qyar.step / gbi5132qyar.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: GOSEMICON datasheet (32 pp, sha256 8f1efc80c6ccbef0, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF