master
John Lauer Publish thermal bottleneck planner, accepted candidate, analysis and native recording scripts 0049da5 29d ago
import json,subprocess
from pathlib import Path
P=Path(__file__).resolve().parent;E=P/'edit';E.mkdir(exist_ok=True)
chapters=[
('intro','Astra fixes the heat-flow bottleneck',"You spotted the limitation in the previous Fusion video. A large copper pour can still be a poor heatsink when another trace cuts almost all the way through it. This time Astra uses the thermal result to revise the routing itself, on a preserved copy of the same board.",['Video 11 is the baseline','Thermal analysis drives routing','Native Fusion / CRR']),
('neck','A cool lobe can mean poor heat flow',"Look at this narrow connection in the VAC one region. The distant copper stays cooler because heat struggles to reach it. In the last pass I kept every route fixed. Now I identify the obstructing net, check alternate layers, and calculate a replacement before drawing it in Fusion.",['Copper area alone is insufficient','Identify the obstructing net','Precomputed route / live edits']),
('N1','N$1 moves to inner layer 15',"The long vertical obstruction is net N dollar one, between R nine and jumper J P two. It is part of the input MOSFET control wiring, not a high current supply. Astra removes its bottom segments and draws the replacement on inner layer fifteen with horizontal, vertical and forty five degree segments. Existing plated connections already reach that layer, so no new via holes are necessary.",['N$1: R9.2 to JP2.P1','Bottom → inner layer 15','Existing via / plated pad reused']),
('VUSB','Remove another cut through VAC1',"This second connection is V U S B, a supply net, not the USB differential data pair. Moving this short section to layer fifteen removes another slot through the VAC one heatsink. Its width and length stay the same. I keep the actual board stackup, and refill native copper after the move.",['VUSB supply branch','Same length and width','Native RATSNEST refill']),
('PGND','Free the lower VAC2 region',"Several connector ground runs divide the lower VAC two copper. I relocate these selected sections to inner layer two, keeping their widths and connecting through the existing plated pads. The thermal ground region for the charger and regulator stays intact. I do not move switching nodes or blindly give every signal a new layer.",['Selected PGND connector runs','Bottom → inner layer 2','Charger / regulator cooling retained']),
('heat','More useful copper, better heat flow',"The comparison holds source copper at sixty five degrees, ambient at twenty five, and keeps the same thirty five micron copper and surface assumptions. Calculated bottom heat flow rises from fifty four to seventy two milliwatts on VAC one, about thirty three percent. V bus improves about eight percent, and VAC two about nine percent. These are bottom heat-path estimates, not measured temperatures or a new board power rating.",['VAC1: 54 → 72 mW / +33%','VBUS: 78 → 85 mW / +8%','VAC2: 57 → 62 mW / +9%']),
('tradeoffs','Check what the reroute costs',"The N dollar one route becomes longer, from fourteen to twenty seven millimeters. The new inner traces also consume some ground-plane area. A geometric reference-plane check is not signal-integrity qualification. The attempted SDA relocation did not find an acceptable path, so SDA stays unchanged. The chosen candidate improves heat spreading while leaving those electrical limitations explicit.",['N$1 length: 14.3 → 26.7 mm','Inner ground area tradeoff','SDA retained after failed search']),
('final','Native checks and reusable engineering',"The recorded board has zero airwires, zero warnings, and no new design-rule errors. One inherited clearance error remains. Astra calculated the reroute; Adom Bridge performed the native edits and checks. The workflow now lives in shared, AI-neutral EDA engineering skills: inspect the bottleneck, reroute suitable traces, refill, compare, checkpoint, and close the scratch document.",['89 vias / 12 pours retained','0 new DRC errors / 1 inherited','Shared EDA engineering skills'])]
voices=[]
for key,title,speech,lines in chapters:
 f=E/(key+'.txt');f.write_text(speech);audio=E/(key+'.mp3')
 if not audio.exists():subprocess.run(['adom-tts','say','@'+str(f),'--out',str(audio)],check=True,stdout=subprocess.DEVNULL)
 dur=float(subprocess.check_output(['ffprobe','-v','error','-show_entries','format=duration','-of','default=nw=1:nk=1',str(audio)]))
 voices.append({'key':key,'title':title,'speech':speech,'lines':lines,'audio':str(audio),'duration':dur});(E/'voices.json').write_text(json.dumps(voices,indent=2));print(key,round(dur,1),flush=True)