component
FR9855SP
Public Made by Adomby adom
Fitipower Integrated Tech DC-DC Converters, SOIC-8-EP. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownFR9855SP
Fitipower Integrated Tech · DC-DC Converters · SOIC-8-EP
FR9855SP from Fitipower Integrated Tech, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SHDN | input | Active-low shutdown / enable and mode-select input. SHDN=0V shuts the device down; 1.5V-2.5V selects forced PWM mode; >3.5V selects power-saving (PSM) mode. Tie to VIN through a 100kΩ resistor for self-startup in power-saving mode. Absolute max 20V; VIH(min)=1.5V, VIL(max)=0.5V. |
| 2 | FB | input | Voltage feedback input. Connect to VOUT via a resistive divider; the loop regulates FB to VFB = 0.765V (typ, 0.75V-0.78V). Feedback input current is 0.01µA typ. |
| 3 | PG | output | Open-drain power-good output. Pulls low when VFB is below ~85% of Vref (falling) and releases above ~90% (rising). Sink capability ~4mA. Requires an external pull-up resistor. |
| 4 | SS | passive | Soft-start pin. Connect a capacitor from SS to GND to program the soft-start ramp period; the pin sources ~6µA (ISS) into the capacitor. |
| 5 | GND | power_in | Signal / power ground return. |
| 6 | LX | output | Switching node between the internal high-side (70mΩ) and low-side (38mΩ) power MOSFETs. Connect the external inductor here. Absolute max -0.3V to VIN+0.3V (transient -5V to VIN+5V for 15ns). |
| 7 | BST | passive | High-side gate-drive bootstrap pin. Connect a 0.1µF-1µF capacitor from BST to LX to fully enhance the internal high-side NMOS. Absolute max VBST = VLX + 6.5V. |
| 8 | VIN | power_in | Power supply input, 4.5V to 18V operating (absolute max 20V). Place input decoupling capacitors as close as possible to VIN and GND to minimize noise coupling. |
| 9 | EP | power_in | Exposed thermal pad on the package underside. Must be soldered to a large PCB copper area tied to GND for maximum power dissipation (θJA = 60°C/W, θJC = 15°C/W). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Fitipower Integrated Tech |
| Package | SOIC-8-EP |
| Category | PMIC |
| Pins | 9 |
Ordering variants
Same part, different packaging or reel option.
FR9855SPFR9855SPDA
CAD (KiCad official)
- Symbol:
FR9855SP - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files:
fr9855sp-etched.step/fr9855sp-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);fr9855sp.step/fr9855sp.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Fitipower Integrated Tech datasheet (16 pp, sha256
b6dded9e25acc343, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).