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FQD7N10LTM

UMW · MOSFETs · TO-252

FQD7N10LTM from UMW, in a TO-252. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G input GATE: MOSFET gate; gate-source voltage is rated ±20 V (VGSS), per the absolute maximum ratings.
2 D passive DRAIN: MOSFET drain; drain-source voltage is rated 100 V (VDSS) and continuous drain current 5.8 A at TC=25°C.
3 S passive SOURCE: MOSFET source; reference terminal for the gate-source voltage rating of ±20 V (VGSS).

Key specifications

Parameter Value
Manufacturer UMW
Package TO-252
Category Transistors/Thyristors
Pins 3

CAD (KiCad official)

  • Symbol: FQD7N10LTM
  • Footprint: Package_TO_SOT_SMD:TO-252-2
  • 3D model: TO-252 (KiCad packages3D, STEP)
  • 3D model files: fqd7n10ltm-etched.step / fqd7n10ltm-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); fqd7n10ltm.step / fqd7n10ltm.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: UMW datasheet (10 pp, sha256 ff67da65fa98560a, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF