# FM33LG023A

**FUDAN MICRO** · Microcontroller Units (MCUs/MPUs/SOCs) · QFN-32(5x5)

FM33LG023A from FUDAN MICRO, in a QFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PD8 | bidirectional | GPIO that also serves as UART3_TX and SWIO (SWD data). |
| 2 | NRST | input | Reset pin with 5 kΩ typical pull-up, VIL max 0.3VDD, VIH min 0.7VDD. |
| 3 | PA13 | bidirectional | GPIO with UART0_RX, LPUART0_RX and ADC_IN4 functions. |
| 4 | PA14 | bidirectional | GPIO with UART0_TX, LPUART0_TX and ADC_IN11 functions. |
| 5 | PA6 | bidirectional | GPIO with COM6/SEG30 LCD drive, OPA1_INN2 and CAN_RX functions. |
| 6 | PA7 | bidirectional | GPIO with COM7/SEG31 LCD drive, OPA1_INP2 and CAN_TX functions. |
| 7 | PA8 | bidirectional | GPIO with SEG0 LCD, LPT32_CH1, SPI1_SSN and COMP2_INP1 functions. |
| 8 | PA9 | bidirectional | GPIO with SEG1 LCD, LPT32_CH2, SPI1_SCK and COMP2_INP2 functions; the QFN32 figure shows PA11 (SEG32/SCL/LPUART2_RX) sharing this pin. |
| 9 | PB0 | bidirectional | GPIO with SEG34 LCD, UART3_RX, SPI1_MISO and OPA1_OUT3 functions; the QFN32 figure shows PA12 (SEG33/SDA/LPUART2_TX) sharing this pin. |
| 10 | PB1 | bidirectional | Pin with SEG35 LCD, UART3_TX, SPI1_MOSI and OPA1_OUT4 functions. |
| 11 | PB4 | bidirectional | GPIO with SEG3 LCD, ATIM_CH1, LPUART2_RX and COMP3_INN1 functions. |
| 12 | PB5 | bidirectional | GPIO with SEG4 LCD, ATIM_CH2, LPUART2_TX and COMP3_INN2 functions. |
| 13 | PB7 | bidirectional | GPIO with SEG6 LCD, ATIM_CH4, SPI2_SCK and ANATST (factory test) functions; PB8 (SEG7/SPI0_SSN/ATIM_CH3N/COMP1_INP1) shares this pin in the QFN32 figure. |
| 14 | PB10 | bidirectional | GPIO with SEG9 LCD, OPA1_INN1, SPI0_MISO and GPT0_CH1 functions. |
| 15 | PB11 | bidirectional | GPIO with SEG10 LCD, OPA1_INP1, SPI MOSI and GPT0_CH2 functions. |
| 16 | PB12 | bidirectional | GPIO with WKUP3 wake-up, FOUT1 clock output, ATIM_ETR and OPA1_OUT1 functions; PE1 (SEG37/SPI0_SCK) shares this pin in the QFN32 figure. |
| 17 | PC2 | bidirectional | GPIO with XTHIN high-frequency crystal input, UART1_RX and LPUART1_RX; PD12 (VDISP1/SDA/SPI2_MOSI) shares this pin in the QFN32 figure. |
| 18 | PC3 | bidirectional | GPIO with XTHOUT high-frequency crystal output, UART1_TX and LPUART1_TX functions. |
| 19 | PC5 | bidirectional | GPIO with SEG14 LCD, DAC_OUT, COMP2_OUT and UART5_TX functions (ESD HBM rating ±2000 V on DAC_OUT). |
| 20 | PC7 | bidirectional | GPIO with SEG16 LCD, SPI2_SSN and ADC_IN6 functions. |
| 21 | PC8 | bidirectional | GPIO with SEG17 LCD, SPI2_SCK and ADC_IN13 functions. |
| 22 | PC9 | bidirectional | GPIO with SEG18 LCD, SPI2_MISO and ADC_IN14 functions. |
| 23 | PC10 | bidirectional | GPIO with WKUP5 wake-up, SEG19 LCD, SPI2_MOSI and ADC_IN15 functions. |
| 24 | XT32KO | output | 32768 Hz crystal oscillator output pin. |
| 25 | XT32KI | input | 32768 Hz crystal oscillator input pin. |
| 26 | VDD15 | power_out | LDO output, connect a 100 nF capacitor to ground. |
| 27 | VSS | power_in | Ground (also VSSA). |
| 28 | VDD | power_in | Power supply (also VDDA), operating range 1.65 V to 5.5 V. |
| 29 | VREFP | passive | Reference voltage pin. |
| 30 | PD11 | bidirectional | GPIO with WKUP6 wake-up, FOUT0 clock output, ATIM_BRK1 and ADC_IN0 functions; PD0 (SEG22/UART5_RX/GPT2_CH1/ADC_IN7) shares this pin in the QFN32 figure. |
| 31 | PD1 | bidirectional | GPIO with SEG23 LCD, UART5_TX, GPT2_CH2 and ADC_IN1 functions; PD6 (WKUP7/ANATST/ATIM_BRK2/ADC_IN10) shares this pin per the QFN32 figure. |
| 32 | PD7 | bidirectional | GPIO that also serves as UART3_RX and SWCLK (SWD clock). |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | FUDAN MICRO |
| Package | QFN-32(5x5) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 33 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (VDD, VDDA) | VDD-VSS | -0.3 |  | 6.5 | V |  | 61 |
| Pin voltage | VPIN |  |  | 6.5 | V | min printed as VSS-0.3 | 61 |
| ADC reference voltage | VREFP-VREFN | -0.3 |  | 6.5 | V |  | 61 |
| Voltage difference between all ground pins | /ΔVSS/ |  |  | 50 | mV |  | 61 |
| Operating temperature | TA | -40 |  | 105 | ℃ | AEC-Q100 grade2 | 61 |
| Storage temperature | TSTG | -55 |  | 150 | ℃ |  | 61 |
| ESD HBM, PC5 (DAC_OUT) | HBM | -2000 |  | 2000 | V | TA=25℃, JEDEC JS-001 | 61 |
| ESD HBM, all other pins | HBM | -4000 |  | 4000 | V | TA=25℃, JEDEC JS-001 | 61 |
| ESD CDM | CDM | -1000 |  | 1000 | V | TA=25℃, JEDEC JS-002 | 61 |
| IO latchup | LU | -210 |  | 210 | mA | -(0.5VDD) < VI < (1.5VDD), TA=25℃, JESD78E | 61 |
| Max current into VDD (source) | ΣIVDD |  |  | 120 | mA |  | 61 |
| Max current out of VSS (sink) | ΣIVSS |  |  | 100 | mA |  | 61 |
| Total IO sink current | ΣIIO |  |  | 100 | mA | all IO sink | 61 |
| Total IO source current | ΣIIO |  |  | 120 | mA | all IO source | 61 |
| AHB clock frequency | fHCLK | 0 |  | 64 | MHz | TA=-40~105C | 62 |
| APB clock frequency | fPCLK | 0 |  | 64 | MHz | TA=-40~105C | 62 |
| Operating voltage range | VDD | 1.65 |  | 5.5 | V | TA=-40~105C | 62 |
| Backup supply voltage, no power switching | VBAT | 1.5 |  | 5.5 | V | power switching not used, shorted to VDD | 62 |
| Backup supply voltage, with power switching | VBAT | 1.5 |  | 4.2 | V | power switching used, VBAT supplied separately | 62 |
| Junction temperature | TJ | -40 |  | 125 | °C |  | 62 |
| Run mode current 8MHz | IDDRUN |  | 1.36 | 1.65 | mA | fAHB=8MHz (RCHF), PLL off, Flash 0 wait, TA=25℃ | 62 |
| Run mode current 8MHz | IDDRUN |  | 1.4 | 1.7 | mA | fAHB=8MHz (RCHF), PLL off, Flash 0 wait, TA=105℃ | 62 |
| Run mode current 16MHz | IDDRUN |  | 2.19 | 2.4 | mA | fAHB=16MHz (RCHF), PLL off, Flash 0 wait, TA=25℃ | 62 |
| Run mode current 16MHz | IDDRUN |  | 2.2 | 2.5 | mA | fAHB=16MHz (RCHF), PLL off, Flash 0 wait, TA=105℃ | 62 |
| Run mode current 24MHz | IDDRUN |  | 3.15 | 3.5 | mA | fAHB=24MHz (RCHF), PLL off, Flash 0 wait, TA=25℃ | 62 |
| Run mode current 24MHz | IDDRUN |  | 3.12 | 3.6 | mA | fAHB=24MHz (RCHF), PLL off, Flash 0 wait, TA=105℃ | 62 |
| Run mode current 64MHz | IDDRUN |  | 5.66 | 6 | mA | fAHB=64MHz, PLL on, Flash 1 wait, TA=25℃ | 62 |
| Run mode current 64MHz | IDDRUN |  | 5.73 | 6.2 | mA | fAHB=64MHz, PLL on, Flash 1 wait, TA=105℃ | 62 |
| Run mode current 614KHz | IDDRUN |  | 137 | 150 | uA | fAHB=614KHz (RCLF), PLL off, Flash 0 wait, TA=25℃ | 62 |
| Run mode current 614KHz | IDDRUN |  | 179 | 200 | uA | fAHB=614KHz (RCLF), PLL off, Flash 0 wait, TA=105℃ | 62 |

## CAD (KiCad official)

- Symbol: `FM33LG023A`
- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`
- 3D model: QFN-32(5x5) (KiCad packages3D, STEP)
- 3D model files: `fm33lg023a-etched.step` / `fm33lg023a-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `fm33lg023a.step` / `fm33lg023a.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [FUDAN MICRO datasheet](docs/fm33lg023a-datasheet.pdf) (100 pp, sha256 `bfd0cc3c1ded70af`, retrieved 2026-10-22, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/fm33lg023a-datasheet.pdf)