main
Ray fgl40n120andtu: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) 6425902 1mo ago
{
  "schema_version": 1,
  "type": "component",
  "slug": "fgl40n120andtu",
  "title": "FGL40N120ANDTU",
  "brief": "onsemi IGBT Transistors / Modules, TO-264-3. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "transistors-thyristors",
    "fgl40n120andtu",
    "factory-2.0.0",
    "extractor-text"
  ],
  "component": {
    "mpn": "FGL40N120ANDTU",
    "manufacturer": "onsemi",
    "package": "TO-264-3",
    "pin_count": 3,
    "category": "Transistors/Thyristors",
    "subcategory": "IGBT Transistors / Modules",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588887232698044416",
    "parts": {
      "symbol": "fgl40n120andtu.kicad_sym",
      "footprint": "fgl40n120andtu.kicad_mod",
      "model_3d": "fgl40n120andtu-etched.glb",
      "model_3d_plain": "fgl40n120andtu.glb",
      "model_3d_step": "fgl40n120andtu-etched.step",
      "model_3d_step_plain": "fgl40n120andtu.step",
      "lbr": "fgl40n120andtu.lbr"
    },
    "distributor_links": {
      "lcsc": "C11754"
    },
    "pins": [
      {
        "number": "1",
        "name": "Gate",
        "type": "input",
        "description": "Gate control input accepting gate-emitter voltage from -25V to +25V; typical threshold voltage is 5.5V at IC = 250µA to initiate collector current conduction."
      },
      {
        "number": "2",
        "name": "Collector",
        "type": "power_in",
        "description": "High-voltage power input terminal rated for 1200V collector-emitter voltage with maximum continuous collector current of 64A at 25°C case temperature."
      },
      {
        "number": "3",
        "name": "Emitter",
        "type": "power_out",
        "description": "Low-voltage power return terminal serving as both the collector current return path and reference potential for gate drive signal control; integral FRD with 75ns typical reverse recovery time."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.2",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.2",
        "primary_model": "claude-haiku-4-5-20251001",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-4-6",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [],
        "pages_sent": 9,
        "cost_usd": 0.2036,
        "at": "2026-09-17T23:28:50"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588887232698044416",
        "pages": 9,
        "sha256": "21de722b92b8814a",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 3,
        "described": 3,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "fgl40n120andtu.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "body on z = 0, through-hole leads below",
        "extents_mm": [
          20.2,
          5.0,
          46.0
        ],
        "zmin_mm": -17.5,
        "centre_offset_mm": 0.975,
        "footprint_binding": "identity",
        "sha256": "2f655d17fcf3ca071707e915b26ff2c4d479479ea3ec290f938ce5750dab9c1f",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "fgl40n120andtu-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "body on z = 0, through-hole leads below",
        "extents_mm": [
          20.2,
          5.0,
          46.0
        ],
        "zmin_mm": -17.5,
        "centre_offset_mm": 0.975,
        "footprint_binding": "identity",
        "sha256": "f450d36df8bd5b3f19b9d1833a7f534c739c04d2763c1fe9bd047436157a14de",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "onsemi",
      "Package": "TO-264-3",
      "Category": "Transistors/Thyristors",
      "Pins": "3"
    }
  },
  "variants": [],
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "fgl40n120andtu"
  ],
  "discovery_pitch": "FGL40N120ANDTU (onsemi) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "fgl40n120andtu.kicad_sym",
    "fgl40n120andtu.kicad_mod",
    "fgl40n120andtu.glb",
    "fgl40n120andtu.step",
    "fgl40n120andtu.lbr",
    "docs/hero.png",
    "docs/fgl40n120andtu-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html"
  ],
  "visibility": {
    "public": true
  },
  "updated_at": "2026-09-24T20:35:14.334Z"
}