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README.md models.json in adom/models@1 tool format with thumbnails · John Lauer 2d ago

FGH200MAAMD

Quectel · Wi-Fi HaLow (IEEE 802.11ah) modules · LGA-38, 11.0 x 10.0 x 2.0 mm, 1.0 mm pitch

Quectel FGH200MAAMD (FGH200M) Wi-Fi HaLow IEEE 802.11ah module on the Morse Micro MM8108, 850 to 950 MHz, SDIO 2.0 / SPI and USB 2.0, 11.0 x 10.0 x 2.0 mm 38-pad LGA. Preliminary data.

Preliminary. The pin table, footprint and electrical values come from Quectel's FGH200M Hardware Design v0.1, a draft (public as the FCC user-manual exhibit for FCC ID XMR2025FGH200M), and the V1.0.0 preliminary specification. RF figures there are still TBD. Check every value against the released Quectel documents before production.

Key specifications

Parameter Value Source
Standard IEEE 802.11ah (Wi-Fi HaLow), 1x1, AP / STA Spec p.2
Chipset Morse Micro MM8108 HD v0.1
Frequency band 850 MHz to 950 MHz, 1/2/4/8 MHz channels Spec p.1-2
Max output power 26 dBm (Quectel spec); FCC grant 0.9311 W conducted max, 908 to 924 MHz Spec p.1; FCC grant
Max PHY rate 43.3 Mbps Spec p.2
Host interfaces SDIO 2.0 / SPI x1, USB 2.0 x1 Spec p.2
VBAT / VBAT_TX 3.0 V to 3.6 V, 3.3 V typ Spec p.2; HD Table 6
VDD_IO 2.25 V to 3.6 V, 3.3 V typ Spec p.2
Operating temperature -40 C to +85 C Spec p.2
Size / weight 11.0 x 10.0 x 2.0 mm, about 0.51 g Spec p.2
RF sensitivity / TX power per MCS TBD in the preliminary documents Spec p.2

Pinout

Pin Name Type Function
1 GND power_in Ground
2 ANT_WIFI passive Wi-Fi HaLow antenna interface, 50 ohm (AIO). Route as a 50 ohm line to the antenna or an RF connector; Quectel shows a pi matching network (series 0 ohm, two shunt positions not mounted) and an optional DC block.
3 GND power_in Ground
4 RESET_N input Reset the module, active low (DI)
5 WAKEUP_IN input Wake up the module (DI). Quectel's text puts it in the VDD_IO domain and, if power saving is unused, pulls it up through 10 kohm to VDD_IO (its figures show VBAT).
6 JTAG_TMS input JTAG test mode select. Quectel: external 10 kohm pull-down.
7 JTAG_TCK input JTAG test clock. Quectel: external 10 kohm pull-down.
8 JTAG_TDO output JTAG test data output
9 JTAG_TDI input JTAG test data input. Quectel: external 10 kohm pull-down.
10 VBAT power_in Module power supply, 3.0 V to 3.6 V (3.3 V typ), at least 0.5 A capability. Quectel shows 10 uF + 100 nF.
11 GND power_in Ground
12 SDIO_DATA0 bidirectional SDIO data 0 / SPI MISO. Quectel: 10 kohm to 100 kohm (47 kohm recommended) pull-up to VDD_IO.
13 SDIO_DATA3 bidirectional SDIO data 3 / SPI CS. Quectel: 47 kohm pull-up to VDD_IO.
14 SDIO_DATA1 bidirectional SDIO data 1 / SPI interrupt. Quectel: 47 kohm pull-up to VDD_IO.
15 SDIO_DATA2 bidirectional SDIO data 2. Quectel: 47 kohm pull-up to VDD_IO (also in SPI mode).
16 SDIO_CMD bidirectional SDIO command / SPI MOSI. Quectel: 47 kohm pull-up to VDD_IO.
17 SDIO_CLK input SDIO clock / SPI clock. No pull-up.
18 GPIO5 bidirectional General-purpose I/O. Quectel: pull down through 10 kohm if unused.
19 GPIO4 bidirectional General-purpose I/O. Quectel: pull down through 10 kohm if unused.
20 GND power_in Ground
21 GPIO3 bidirectional General-purpose I/O. Quectel: pull down through 10 kohm if unused.
22 VDD_IO power_in I/O power supply, 2.25 V to 3.6 V per the electrical table (the pin table says 3.0 V to 3.6 V), 3.3 V typ; must not exceed VBAT. Quectel shows 100 nF.
23 GND power_in Ground
24 VBAT_TX power_in RF power amplifier supply, 3.0 V to 3.6 V (3.3 V typ), at least 1.0 A capability. Quectel shows 10 uF + 100 nF.
25 VDD_USB power_in USB supply, 3.0 V to 3.6 V (3.3 V typ). Quectel shows 10 uF + 100 nF.
26 GND power_in Ground
27 USB_DM bidirectional USB 2.0 D- (90 ohm differential). Leave open when the SDIO/SPI host interface is used.
28 USB_DP bidirectional USB 2.0 D+ (90 ohm differential). Leave open when the SDIO/SPI host interface is used.
29 GPIO2/BUSY output GPIO2. In power-saving mode this is the BUSY output to the host (CMOS input). Quectel's figures show a 10 kohm pull-down when unused.
30 GND power_in Ground
31 GPIO1 bidirectional General-purpose I/O. Quectel: pull down through 10 kohm if unused.
32 GPIO0 bidirectional General-purpose I/O. Quectel: pull down through 10 kohm if unused.
33 GPIO6 bidirectional General-purpose I/O. Quectel: pull down through 10 kohm if unused.
34 GPIO7 bidirectional General-purpose I/O. Quectel: pull down through 10 kohm if unused.
35 GPIO8 bidirectional General-purpose I/O. Quectel: pull down through 10 kohm if unused.
36 GPIO9 bidirectional General-purpose I/O. Quectel: pull down through 10 kohm if unused.
37 GPIO10 bidirectional General-purpose I/O. Quectel: pull down through 10 kohm if unused.
38 GND power_in Ground

Source: HD v0.1 sec 4.1 Fig 1 Pin Assignment (top view, p.14) + Table 6 Pin Description (pp.15-17) + sec 4.4 Figs 3-5 (BUSY = GPIO2).

Footprint and pin 1

The v0.1 draft draws the pin-1 corner two ways: its Fig. 19 (recommended footprint) labels pin 1 at the top right, the same as the Fig. 18 bottom view, while its Fig. 1 and Fig. 17 (top views) and Fig. 20 (top marking) put pin 1 at the top left. The Morse Micro MM8108-MF15457 data sheet, which has the same 38-pad layout, also shows pin 1 at the top left in its top-view pin diagram. This footprint therefore puts pin 1 at the TOP LEFT (top view, as placed on the PCB); pins 1 to 11 run left to right along the top edge and the numbering continues clockwise (12 to 20 down the right side, 21 to 30 along the bottom, 31 to 38 up the left side). Confirm against the released Quectel hardware design before production.

Land pattern source: HD v0.1 sec 6.2 Fig 19 Recommended Footprint (p.35) + Fig 18 bottom dimensions (p.34).

Dimension Value (mm)
pad 0.6 x 0.6 square
pitch 1.0 (10 x 1 mm = 10 mm across, 9 x 1 mm = 9 mm down)
pads centred on body rows y=+-4.5, columns x=+-5.0
body 11.0 x 10.0 nominal (+0.3/-0.15)

3D models

No manufacturer 3D model was available, so the model is AI-created: built by Adom from the datasheet drawing (HD v0.1 sec 6.1 Fig 17 (p.33): 11 x 10 x 2.0, substrate 0.6; Fig 20 (top marking dot top-left)). It is a simplified body (substrate, shield or lid, and the contact pads), Z-up and seated on z = 0, centred on the footprint origin.

Simplifications and assumptions: No Quectel STEP available (documents behind login / not in FCC filing); No U.FL on the module (FCC external photos: shield top, LGA bottom only).

File What it is
fgh200maamd.step / fgh200maamd.glb Plain model
fgh200maamd-etched.step / fgh200maamd-etched.glb The same model with the MPN as a virtual laser mark (top face, adom-aiflow-etch, gate PASS). This is the board/library model.
fgh200maamd-hero.glb The page's 3D view: the marked model plus teal dashed pad outlines, silkscreen with pin 1 and signal names (adom-hero 1.4). Not for boards.

The MPN mark is an identification aid added by Adom, not a claim about the manufacturer's real marking.

Sourcing

Distributor Part number
Mouser 277-FGH200MAAMD
DigiKey 2958-FGH200MAAMDTR-ND
LCSC not listed

Snapshot 2026-10-17 (adom-parts-search): Mouser 277-FGH200MAAMD: 0 in stock (new product, 154 days lead time), USD 21.18 (1 pc), USD 16.23 (100). DigiKey 2958-FGH200MAAMDTR-ND: 0 in stock, USD 21.51. LCSC: not listed.

Manufacturer and resources

Manufacturer documents are linked, not copied: their terms do not allow redistribution.

Provenance

File Classification Source
fgh200maamd.kicad_sym source-derived HD v0.1 sec 4.1 Fig 1 Pin Assignment (top view, p.14) + Table 6 Pin Description (pp.15-17) + sec 4.4 Figs 3-5 (BUSY = GPIO2)
fgh200maamd.kicad_mod source-derived HD v0.1 sec 6.2 Fig 19 Recommended Footprint (p.35) + Fig 18 bottom dimensions (p.34)
fgh200maamd.step AI-created HD v0.1 sec 6.1 Fig 17 (p.33): 11 x 10 x 2.0, substrate 0.6; Fig 20 (top marking dot top-left)
fgh200maamd-etched.step derived (virtual MPN mark added) fgh200maamd.step
fgh200maamd.glb derived (format conversion) fgh200maamd.step
fgh200maamd-etched.glb derived (format conversion) fgh200maamd-etched.step
fgh200maamd-hero.glb derived (annotated presentation model, not for board use) fgh200maamd-etched.glb, fgh200maamd.kicad_mod, page.json component.pins
fgh200maamd.lbr derived fgh200maamd.kicad_sym, fgh200maamd.kicad_mod

Every file's SHA-256, the source documents with their hashes and retrieval dates, the dimensions used and the assumptions are in provenance/provenance.json. The MPN mark plan and gate result are in provenance/.

Found a wrong pin, pad or dimension? Open an issue on this page with the file name and hash, the disputed value, the source page and a screenshot.

License

Adom-authored files: CC BY-SA 4.0. See LICENSE.