component

FDS3672

Public Made by Adom

by adom

onsemi MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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FDS3672

onsemi · MOSFETs · SO-8

FDS3672 from onsemi, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S passive Source of the N-channel MOSFET, tied with pins 2 and 3 in the package diagram.
2 S passive Source of the N-channel MOSFET, tied with pins 1 and 3 in the package diagram.
3 S passive Source of the N-channel MOSFET, tied with pins 1 and 2 in the package diagram.
4 G input Gate of the N-channel MOSFET; VGS maximum rating is ±20 V.
5 D passive Drain of the MOSFET, tied with pins 6, 7 and 8; VDSS is 100 V.
6 D passive Drain of the MOSFET, tied with pins 5, 7 and 8; VDSS is 100 V.
7 D passive Drain of the MOSFET, tied with pins 5, 6 and 8; VDSS is 100 V.
8 D passive Drain of the MOSFET, tied with pins 5, 6 and 7; VDSS is 100 V.

Key specifications

Parameter Value
Manufacturer onsemi
Package SO-8
Category Transistors/Thyristors
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain to Source Voltage VDSS 100 V 2
Gate to Source Voltage VGS -20 20 V 2
Drain Current, Continuous ID 7.5 A TA = 25oC, VGS = 10V, RθJA = 50oC/W 2
Drain Current, Continuous ID 4.8 A TA = 100oC, VGS = 10V, RθJA = 50oC/W 2
Single Pulse Avalanche Energy EAS 416 mJ Note 1 2
Power Dissipation PD 2.5 W 2
Operating and Storage Temperature TJ, TSTG -55 150 oC 2
Thermal Resistance, Junction to Ambient RθJA 50 oC/W at 10 seconds (Note 3) 2
Thermal Resistance, Junction to Ambient RθJA 85 oC/W at 1000 seconds (Note 3) 2
Thermal Resistance, Junction to Case RθJC 25 oC/W Note 2 2
Drain to Source Breakdown Voltage BVDSS 100 V ID = 250µA, VGS = 0V 3
Zero Gate Voltage Drain Current IDSS 1 µA VDS = 80V, VGS = 0V 3
Zero Gate Voltage Drain Current IDSS 250 µA VDS = 80V, VGS = 0V, TC = 150oC 3
Gate to Source Leakage Current IGSS -100 100 nA VGS = ±20V 3
Gate to Source Threshold Voltage VGS(TH) 2 4 V VGS = VDS, ID = 250µA 3
Drain to Source On Resistance rDS(ON) 0.019 0.023 Ω ID = 7.5A, VGS = 10V 3
Drain to Source On Resistance rDS(ON) 0.023 0.028 Ω ID = 6.8A, VGS = 6V 3
Drain to Source On Resistance rDS(ON) 0.035 0.043 Ω ID = 7.5A, VGS = 10V, TC = 150oC 3
Total Gate Charge at 10V Qg(TOT) 28 37 nC VGS = 0V to 10V, VDD = 50V, ID = 7.5A, Ig = 1.0mA 3
Threshold Gate Charge Qg(TH) 4 6 nC VGS = 0V to 2V 3
Turn-On Time tON 51 ns VDD = 50V, ID = 4A, VGS = 10V, RGS = 10Ω 3
Turn-Off Time tOFF 96 ns VDD = 50V, ID = 4A, VGS = 10V, RGS = 10Ω 3
Source to Drain Diode Voltage VSD 1.25 V ISD = 7.5A 3
Source to Drain Diode Voltage VSD 1 V ISD = 4A 3
Reverse Recovery Time trr 55 ns ISD = 7.5A, dISD/dt = 100A/µs 3
Reverse Recovered Charge QRR 90 nC ISD = 7.5A, dISD/dt = 100A/µs 3
Input Capacitance CISS 2015 pF VDS = 25V, VGS = 0V, f = 1MHz 3
Output Capacitance COSS 285 pF VDS = 25V, VGS = 0V, f = 1MHz 3
Reverse Transfer Capacitance CRSS 70 pF VDS = 25V, VGS = 0V, f = 1MHz 3
Gate to Source Gate Charge Qgs 10 nC VDD = 50V, ID = 7.5A, Ig = 1.0mA 3
Gate Charge Threshold to Plateau Qgs2 6.8 nC VDD = 50V, ID = 7.5A, Ig = 1.0mA 3
Gate to Drain Miller Charge Qgd 6 nC VDD = 50V, ID = 7.5A, Ig = 1.0mA 3
Turn-On Delay Time td(ON) 14 ns VDD = 50V, ID = 4A, VGS = 10V, RGS = 10Ω 3
Rise Time tr 20 ns VDD = 50V, ID = 4A, VGS = 10V, RGS = 10Ω 3
Turn-Off Delay Time td(OFF) 37 ns VDD = 50V, ID = 4A, VGS = 10V, RGS = 10Ω 3
Fall Time tf 27 ns VDD = 50V, ID = 4A, VGS = 10V, RGS = 10Ω 3

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper drain pins. RθJC is guaranteed by design while RθCA is determined by the user’s board design. 3: RθJA is measured with 1.0 in2 copper on FR-4 board 3

CAD (KiCad official)

  • Symbol: FDS3672
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: fds3672-etched.step / fds3672-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); fds3672.step / fds3672.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (9 pp, sha256 01a4e61bbfa21aa8, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF