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F280025CPNQR

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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F280025CPNQR

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-80(12x12)

F280025CPNQR from Texas Instruments, in a LQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GPIO30 bidirectional General-purpose I/O 30 with alternates CANA_RX, SPIB_SIMO, OUTPUTXBAR7, EQEP1_STROBE, FSIRXA_CLK, EPWM1_A and HIC_D8; the internal pullup is disabled by default.
2 GPIO31 bidirectional General-purpose I/O 31 with alternates CANA_TX, SPIB_SOMI, OUTPUTXBAR8, EQEP1_INDEX, FSIRXA_D1, EPWM1_B and HIC_D10; the internal pullup is disabled by default.
3 GPIO29 bidirectional General-purpose I/O 29 with alternates SCIA_TX, EPWM7_B, OUTPUTXBAR6, EQEP1_B, EQEP2_INDEX, LINA_RX, SPIB_STE, I2CB_SCL and HIC_NCS; ERRORSTS use requires an external pulldown resistor.
4 GPIO28 bidirectional General-purpose I/O 28 with alternates SCIA_RX, EPWM7_A, OUTPUTXBAR5, EQEP1_A, EQEP2_STROBE, LINA_TX, SPIB_CLK, I2CB_SDA and HIC_NOE; ERRORSTS use requires an external pulldown resistor.
5 XRSn bidirectional Open-drain device reset input and watchdog reset output with internal pullup; connect a 2.2 kΩ to 10 kΩ resistor between XRSn and VDDIO and a capacitor of 100 nF or less to VSS if filtering is used.
6 GPIO46 bidirectional General-purpose I/O 46 with alternates LINA_TX, FSITXA_D1 and HIC_NWE.
7 VDDIO power_in 3.3 V digital I/O supply pin; see the power management module section for usage.
8 VDD power_in 1.2 V digital logic supply pin, generated internally by VREG; decoupling capacitance is required on VDD.
9 VSS power_in Digital ground; all VSS pins must be connected to board ground.
10 A6 input Analog input A6 (CMPSS-1 comparator inputs and AIO228 alternate); unused analog pins may be left unconnected, tied to VSSA, or tied to VSSA through a resistor.
11 C6 input Analog input C6 (CMPSS-3 comparator input 0 and AIO226 alternate); unused analog pins may be left unconnected, tied to VSSA, or tied to VSSA through a resistor.
12 A3/C5/VDAC input ADC-A input 3 / ADC-C input 5, and optional external reference for the on-chip CMPSS DAC; an internal capacitor to VSSA is always present, and at least one 1 µF capacitor is required if used as the DAC reference.
13 A2/C9 input ADC-A input 2 / ADC-C input 9 with CMPSS-1 comparator inputs and AIO224 alternate.
14 A15/C7 input ADC-A input 15 / ADC-C input 7 with CMPSS-1 comparator inputs and AIO233 alternate.
15 A14/C4 input ADC-A input 14 / ADC-C input 4 with CMPSS-3 comparator inputs and AIO239 alternate.
16 A11/C0 input ADC-A input 11 / ADC-C input 0 with CMPSS-1 comparator inputs and AIO237 alternate.
17 A5/C2 input ADC-A input 5 / ADC-C input 2 with CMPSS-3 comparator inputs and AIO244 alternate.
18 A1 input Analog input A1 (CMPSS-1 comparator input 4 and AIO232 alternate).
19 A0/C15 input ADC-A input 0 / ADC-C input 15 with CMPSS-3 comparator input 2 and AIO231 alternate.
20 VREFHI input ADC high voltage reference: driven externally in external reference mode or by the device in internal reference mode; place at least one 2.2 µF capacitor between VREFHI and VREFLO as close to the device as possible.
21 VREFLO input ADC low voltage reference, connected to VSSA.
22 A12/C1 input ADC-A input 12 / ADC-C input 1 with CMPSS-2 and CMPSS-4 comparator inputs and AIO238 alternate.
23 A7/C3 input ADC-A input 7 / ADC-C input 3 with CMPSS-4 comparator inputs and AIO245 alternate.
24 A8/C11 input ADC-A input 8 / ADC-C input 11 with CMPSS-2 and CMPSS-4 comparator inputs and AIO241 alternate.
25 VSSA power_in Analog ground for the ADC and comparator subsystem.
26 VDDA power_in 3.3 V analog supply pin; a minimum of 2.2 µF decoupling capacitor is required on this pin.
27 A4/C14 input ADC-A input 4 / ADC-C input 14 with CMPSS-2 and CMPSS-4 comparator inputs and AIO225 alternate.
28 A9/C8 input ADC-A input 9 / ADC-C input 8 with CMPSS-2 and CMPSS-4 comparator inputs and AIO227 alternate.
29 A10/C10 input ADC-A input 10 / ADC-C input 10 with CMPSS-2 comparator inputs and AIO230 alternate.
30 VSS power_in Digital ground; all VSS pins must be connected to board ground.
31 VDD power_in 1.2 V digital logic supply pin, generated internally by VREG; decoupling capacitance is required on VDD.
32 VDDIO power_in 3.3 V digital I/O supply pin; see the power management module section for usage.
33 FLT2 unconnected Flash test pin 2 reserved for TI; it must be left unconnected (or tied to VSS through 4.7 kΩ or greater).
34 FLT1 unconnected Flash test pin 1 reserved for TI; it must be left unconnected (or tied to VSS through 4.7 kΩ or greater).
35 GPIO13 bidirectional General-purpose I/O 13 with alternates EPWM7_B, EQEP1_INDEX, PMBUSA_ALERT (open-drain), FSIRXA_CLK, LINB_RX, SPIA_SOMI, CANA_TX and HIC_D11.
36 GPIO12 bidirectional General-purpose I/O 12 with alternates EPWM7_A, EQEP1_STROBE, PMBUSA_CTL, FSIRXA_D0, LINB_TX, SPIA_CLK, CANA_RX and HIC_INT.
37 GPIO11 bidirectional General-purpose I/O 11 with alternates EPWM6_B, OUTPUTXBAR7, EQEP1_B, SPIA_STE, FSIRXA_D1, LINB_RX, EQEP2_A, SPIA_SIMO and HIC_NBE0.
38 GPIO33 bidirectional General-purpose I/O 33 with alternates I2CA_SCL (open-drain), SPIB_STE, OUTPUTXBAR4, LINA_RX, FSIRXA_CLK, CANA_RX, EQEP2_B, ADCSOCAO and HIC_D0.
39 GPIO16 bidirectional General-purpose I/O 16 with alternates SPIA_SIMO, OUTPUTXBAR7, EPWM5_A, SCIA_TX, EQEP1_STROBE, PMBUSA_SCL, XCLKOUT, EQEP2_B and SPIB_SOMI.
40 GPIO17 bidirectional General-purpose I/O 17 with alternates SPIA_SOMI, OUTPUTXBAR8, EPWM5_B, SCIA_RX, EQEP1_INDEX, PMBUSA_SDA, CANA_TX and HIC_D2.
41 GPIO24 bidirectional General-purpose I/O 24 with alternates OUTPUTXBAR1, EQEP2_A, SPIB_SIMO, LINB_TX, PMBUSA_SCL, SCIA_TX, ERRORSTS (requires an external pulldown resistor when used) and HIC_D3.
42 GPIO25 bidirectional General-purpose I/O 25 with alternates OUTPUTXBAR2, EQEP2_B, EQEP1_A, SPIB_SOMI, FSITXA_D1, PMBUSA_SDA, SCIA_RX and HIC_BASESEL0.
43 GPIO26 bidirectional General-purpose I/O 26 with alternates OUTPUTXBAR3, EQEP2_INDEX, SPIB_CLK, FSITXA_D0, PMBUSA_CTL, I2CA_SDA, HIC_D0 and HIC_A1.
44 GPIO27 bidirectional General-purpose I/O 27 with alternates OUTPUTXBAR4, EQEP2_STROBE, SPIB_STE, FSITXA_CLK, PMBUSA_ALERT (open-drain), I2CA_SCL, HIC_D1 and HIC_A4.
45 TCK input JTAG test clock input with an internal pullup resistor.
46 GPIO37/TDO output JTAG test data output (TDO) by default; it is tri-stated when JTAG is inactive, so an internal or external pullup is needed to avoid a floating GPIO input when used as GPIO.
47 TMS bidirectional JTAG test mode select with an internal pullup; the board should include an external 2.2 kΩ pullup to VDDIO to hold JTAG in reset during normal operation.
48 GPIO35/TDI input JTAG test data input (TDI) by default; the internal pullup is disabled by default, so enable it or add an external pullup to avoid a floating input when used as TDI.
49 GPIO32 bidirectional General-purpose I/O 32 with alternates I2CA_SDA (open-drain), SPIB_CLK, LINA_TX, FSIRXA_D0, CANA_TX, ADCSOCBO and HIC_INT.
50 GPIO18_X2 bidirectional General-purpose I/O 18, or crystal oscillator output X2 when the crystal oscillator is used; alternates include SPIA_CLK, CANA_RX, EPWM6_A, I2CA_SCL, XCLKOUT and FSITXA_TDM_CLK.
51 GPIO19_X1 bidirectional General-purpose I/O 19, or crystal/single-ended clock input X1; device initialization software must configure this pin before enabling the crystal oscillator, and it can also be driven by a single-ended 3.3 V clock.
52 VDDIO power_in 3.3 V digital I/O supply pin; see the power management module section for usage.
53 VDD power_in 1.2 V digital logic supply pin, generated internally by VREG; decoupling capacitance is required on VDD.
54 GPIO43 bidirectional General-purpose I/O 43 with alternates OUTPUTXBAR6, PMBUSA_ALERT (open-drain), I2CA_SCL (open-drain), EQEP1_INDEX, CLB_OUTPUTXBAR4 and HIC_A7.
55 VSS power_in Digital ground; all VSS pins must be connected to board ground.
56 GPIO39 bidirectional General-purpose I/O 39 with alternates FSIRXA_CLK, EQEP2_INDEX, CLB_OUTPUTXBAR2, SYNCOUT, EQEP1_INDEX and HIC_D7.
57 GPIO42 bidirectional General-purpose I/O 42 with alternates LINA_RX, OUTPUTXBAR5, PMBUSA_CTL, I2CA_SDA (open-drain), EQEP1_STROBE, CLB_OUTPUTXBAR3 and HIC_D2.
58 GPIO8 bidirectional General-purpose I/O 8 with alternates EPWM5_A, ADCSOCAO, EQEP1_STROBE, SCIA_TX, SPIA_SIMO, I2CA_SCL (open-drain), FSITXA_D1 and HIC_A0.
59 GPIO4 bidirectional General-purpose I/O 4 with alternates EPWM3_A, OUTPUTXBAR3, CANA_TX, SPIB_CLK, EQEP2_STROBE, FSIRXA_CLK, CLB_OUTPUTXBAR6, HIC_BASESEL2 and HIC_NWE.
60 GPIO3 bidirectional General-purpose I/O 3 with alternates EPWM2_B, OUTPUTXBAR2, PMBUSA_SCL (open-drain), SPIA_CLK, SCIA_RX, FSIRXA_D0, I2CB_SCL (open-drain), CANA_RX and HIC_NOE.
61 GPIO2 bidirectional General-purpose I/O 2 with alternates EPWM2_A, OUTPUTXBAR1, PMBUSA_SDA (open-drain), SPIA_SIMO, SCIA_TX, FSIRXA_D1, I2CB_SDA (open-drain), CANA_TX and HIC_A1.
62 GPIO1 bidirectional General-purpose I/O 1 with alternates EPWM1_B, I2CA_SCL (open-drain), SPIA_SOMI, CLB_OUTPUTXBAR7, HIC_A2 and FSITXA_TDM_D1.
63 GPIO0 bidirectional General-purpose I/O 0 with alternates EPWM1_A, I2CA_SDA (open-drain), SPIA_STE, FSIRXA_CLK, CLB_OUTPUTXBAR8 and HIC_BASESEL1.
64 GPIO40 bidirectional General-purpose I/O 40 with alternates SPIB_SIMO, EPWM2_B, PMBUSA_SDA (open-drain), FSIRXA_D0, EQEP1_A, LINB_TX and HIC_NBE1.
65 GPIO23 bidirectional General-purpose I/O 23 with alternates EQEP1_INDEX, SPIB_STE, LINA_RX, LINB_RX, HIC_A3, EPWM4_B and HIC_D11.
66 GPIO41 bidirectional General-purpose I/O 41 with alternates EPWM2_A, PMBUSA_SCL (open-drain), FSIRXA_D1, EQEP1_B, LINB_RX, HIC_A4, SPIB_SOMI and HIC_D12.
67 GPIO22 bidirectional General-purpose I/O 22 with alternates EQEP1_STROBE, SPIB_CLK, LINA_TX, CLB_OUTPUTXBAR1, LINB_TX, HIC_A5, EPWM4_A and HIC_D13.
68 GPIO7 bidirectional General-purpose I/O 7 with alternates EPWM4_B, OUTPUTXBAR5, EQEP1_B, SPIB_SIMO, FSITXA_CLK, CLB_OUTPUTXBAR2, HIC_A6 and HIC_D14.
69 GPIO44 bidirectional General-purpose I/O 44 with alternates OUTPUTXBAR7, EQEP1_A, FSITXA_CLK, CLB_OUTPUTXBAR3, HIC_D7 and HIC_D5.
70 VSS power_in Digital ground; all VSS pins must be connected to board ground.
71 VDD power_in 1.2 V digital logic supply pin, generated internally by VREG; decoupling capacitance is required on VDD.
72 VDDIO power_in 3.3 V digital I/O supply pin; see the power management module section for usage.
73 GPIO45 bidirectional General-purpose I/O 45 with alternates OUTPUTXBAR8, FSITXA_D0, CLB_OUTPUTXBAR4 and HIC_D6.
74 GPIO5 bidirectional General-purpose I/O 5 with alternates EPWM3_B, OUTPUTXBAR3, CANA_RX, SPIA_STE, FSITXA_D1, CLB_OUTPUTXBAR5, HIC_A7, HIC_D4 and HIC_D15.
75 GPIO9 bidirectional General-purpose I/O 9 with alternates EPWM5_B, OUTPUTXBAR6, EQEP1_INDEX, SCIA_RX, SPIA_CLK, FSITXA_D0, LINB_RX, HIC_BASESEL0, I2CB_SCL (open-drain) and HIC_NRDY.
76 GPIO10 bidirectional General-purpose I/O 10 with alternates EPWM6_A, ADCSOCBO, EQEP1_A, SPIA_SOMI, I2CA_SDA (open-drain), FSITXA_CLK, LINB_TX, HIC_NWE and FSITXA_TDM_D0.
77 GPIO34 bidirectional General-purpose I/O 34 with alternates OUTPUTXBAR1, PMBUSA_SDA (open-drain), HIC_NBE1, I2CB_SDA (open-drain) and HIC_D9.
78 GPIO15 bidirectional General-purpose I/O 15 with alternates I2CB_SCL (open-drain), OUTPUTXBAR4, PMBUSA_SCL (open-drain), SPIB_STE, EQEP2_B, LINB_RX, EPWM3_B, CLB_OUTPUTXBAR6 and HIC_D12.
79 GPIO14 bidirectional General-purpose I/O 14 with alternates I2CB_SDA (open-drain), OUTPUTXBAR3, PMBUSA_SDA (open-drain), SPIB_CLK, EQEP2_A, LINB_TX, EPWM3_A, CLB_OUTPUTXBAR7 and HIC_D15.
80 GPIO6 bidirectional General-purpose I/O 6 with alternates EPWM4_A, OUTPUTXBAR4, SYNCOUT, EQEP1_A, SPIB_SOMI, FSITXA_D0, FSITXA_D1, HIC_NBE1 and CLB_OUTPUTXBAR8.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-80(12x12)
Category Embedded Processors & Controllers
Pins 80

CAD (KiCad official)

  • Symbol: F280025CPNQR
  • Footprint: Package_QFP:LQFP-80_12x12mm_P0.5mm
  • 3D model: LQFP-80(12x12) (KiCad packages3D, STEP)
  • 3D model files: f280025cpnqr-etched.step / f280025cpnqr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); f280025cpnqr.step / f280025cpnqr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (245 pp, sha256 0723d8e3e09e1f8b, retrieved 2026-10-12, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF