component

ETA3512FSG

Public Made by Adom

by adom

etasolution DC-DC Converters, SOT-563. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

componentpmiceta3512fsg
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs eta3512fsg: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
eta3512fsg-etched.fit.json eta3512fsg: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
eta3512fsg-etched.glb eta3512fsg: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
eta3512fsg-etched.step eta3512fsg: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
eta3512fsg.glb Publish 0.1.0 · Ray
eta3512fsg.kicad_mod Publish 0.1.0 · Ray
eta3512fsg.kicad_sym Publish 0.1.0 · Ray
eta3512fsg.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
eta3512fsg.step Publish 0.1.0 · Ray
package.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json eta3512fsg: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md eta3512fsg: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray

ETA3512FSG

etasolution · DC-DC Converters · SOT-563

ETA3512FSG from etasolution, in a SOT-563. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 FB input Feedback input. Connect an external resistor divider from VOUT to FB and GND to set the output voltage per VOUT = 0.6V x (1 + R1/R2). Internal reference VREF = 0.6V typical (0.594-0.606V at 25 C).
2 GND power_in Device ground return. Reference for input, output, and control signals.
3 IN power_in Supply voltage input, 2.5V to 5.5V (7.5V abs max). Bypass with a 10uF ceramic capacitor to GND placed as close as possible to the pin.
4 SW power_out Switching node, drain connection of the internal high-side and low-side power MOSFETs. Connect a 1uH inductor between SW and the regulator output. High-side Rds(on) = 100 mOhm typ, low-side Rds(on) = 60 mOhm typ; high-side current limit 4.5A typ.
5 EN input Enable input. Drive high (>=1.2V rising) to enable the converter, low (<=0.4V falling) to disable/shutdown. EN input current ~1uA at VEN=2V. Do not float.
6 PG output Power Good open-drain output. High impedance when the output voltage is within regulation (approximately 90% to 120% of the FB threshold, 5% hysteresis); pulled low otherwise. Requires an external pull-up resistor (e.g. 100k to VIN or logic rail).

Key specifications

Parameter Value
Manufacturer etasolution
Package SOT-563
Category PMIC
Pins 6

Ordering variants

Same part, different packaging or reel option.

  • ETA3512FSG

CAD (KiCad official)

  • Symbol: ETA3512FSG
  • Footprint: Package_TO_SOT_SMD:SOT-563
  • 3D model: SOT-563 (KiCad packages3D, STEP)
  • 3D model files: eta3512fsg-etched.step / eta3512fsg-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); eta3512fsg.step / eta3512fsg.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: etasolution datasheet (10 pp, sha256 cbb8879886b77602, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF