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ESP32-S3R2
Public Made by Adomby adom
Espressif Systems RF and Wireless, 56-VFQFN Exposed Pad. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownESP32-S3R2
Espressif Systems · RF and Wireless · 56-VFQFN Exposed Pad
ESP32-S3R2 from Espressif Systems, in a 56-VFQFN Exposed Pad. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | LNA_IN | bidirectional | Low Noise Amplifier (RF LNA) input/output signal for the 2.4 GHz RF path. |
| 2 | VDD3P3 | power_in | Analog power domain supply input for the chip. |
| 3 | VDD3P3 | power_in | Analog power domain supply input for the chip. |
| 4 | CHIP_PU | input | High enables the chip and low disables (powers down) it; do not leave this pin floating. |
| 5 | GPIO0 | bidirectional | Strapping pin for chip boot mode (with GPIO46), with weak pull-up at reset (default bit value 1). |
| 6 | GPIO1 | bidirectional | General-purpose IO with IO MUX/GPIO Matrix functions and ADC1_CH0/TOUCH1 analog function; default drive 20 mA. |
| 7 | GPIO2 | bidirectional | General-purpose IO with IO MUX/GPIO Matrix functions and ADC1_CH1/TOUCH2 analog function; default drive 20 mA. |
| 8 | GPIO3 | bidirectional | Strapping pin for JTAG signal source selection, floating by default at reset (Table 3-1). |
| 9 | GPIO4 | bidirectional | General-purpose IO with IO MUX/GPIO Matrix functions and ADC1_CH3/TOUCH4 analog function; default drive 20 mA. |
| 10 | GPIO5 | bidirectional | General-purpose IO with IO MUX/GPIO Matrix functions and ADC1_CH4/TOUCH5 analog function; default drive 20 mA. |
| 11 | GPIO6 | bidirectional | General-purpose IO with IO MUX/GPIO Matrix functions and ADC1_CH5/TOUCH6 analog function; default drive 20 mA. |
| 12 | GPIO7 | bidirectional | General-purpose IO with IO MUX/GPIO Matrix functions and ADC1_CH6/TOUCH7 analog function; default drive 20 mA. |
| 13 | GPIO8 | bidirectional | General-purpose IO with IO MUX/GPIO Matrix functions and ADC1_CH7/TOUCH8 analog function; default drive 20 mA. |
| 14 | GPIO9 | bidirectional | General-purpose IO with IO MUX/GPIO Matrix functions and ADC1_CH8/TOUCH9 analog function; default drive 20 mA. |
| 15 | GPIO10 | bidirectional | General-purpose IO with IO MUX/GPIO Matrix functions and ADC1_CH9/TOUCH10 analog function; default drive 20 mA. |
| 16 | GPIO11 | bidirectional | General-purpose IO with IO MUX/GPIO Matrix functions and ADC2_CH0/TOUCH11 analog function; default drive 20 mA. |
| 17 | GPIO12 | bidirectional | General-purpose IO with IO MUX/GPIO Matrix functions and ADC2_CH1/TOUCH12 analog function; default drive 20 mA. |
| 18 | GPIO13 | bidirectional | General-purpose IO with IO MUX/GPIO Matrix functions and ADC2_CH2/TOUCH13 analog function; default drive 20 mA. |
| 19 | GPIO14 | bidirectional | General-purpose IO with IO MUX/GPIO Matrix functions and ADC2_CH3/TOUCH14 analog function; default drive 20 mA. |
| 20 | VDD3P3_RTC | power_in | Supply input for the RTC and part of the digital power domains, including RTC IO pins. |
| 21 | XTAL_32K_P | bidirectional | Positive 32 kHz clock connection to the chip's oscillator, also usable as ADC2_CH4 analog function (RTC_GPIO15). |
| 22 | XTAL_32K_N | bidirectional | Negative 32 kHz external clock input/output, also usable as ADC2_CH5 analog function (RTC_GPIO16). |
| 23 | GPIO17 | bidirectional | General-purpose IO with ADC2_CH6 analog function; default drive strength 10 mA. |
| 24 | GPIO18 | bidirectional | General-purpose IO with ADC2_CH7 analog function; default drive strength 10 mA. |
| 25 | GPIO19 | bidirectional | General-purpose IO that by default serves as USB_D- for the USB Serial/JTAG and USB OTG function; default drive strength 40 mA. |
| 26 | GPIO20 | bidirectional | General-purpose IO that by default serves as USB_D+ for the USB Serial/JTAG and USB OTG function; default drive strength 40 mA. |
| 27 | GPIO21 | bidirectional | General-purpose IO with IO MUX and RTC GPIO functions; default drive strength 20 mA. |
| 28 | SPICS1 | bidirectional | SPI chip select 1 powered by VDD_SPI, used to connect the in-package PSRAM and not recommended for other use. |
| 29 | VDD_SPI | power_out | Backup power line input or regulated output for the in-package flash/PSRAM and SPI IO, configurable as input or output. |
| 30 | SPIHD | bidirectional | SPI hold signal (SIO3 / DQ3) for the in-package flash/PSRAM, powered by VDD_SPI and not for other use. |
| 31 | SPIWP | bidirectional | SPI write-protect signal (SIO2 / DQ2) for the in-package flash/PSRAM, powered by VDD_SPI and not for other use. |
| 32 | SPICS0 | bidirectional | SPI chip select 0 for the in-package flash, powered by VDD_SPI and not for other use. |
| 33 | SPICLK | bidirectional | SPI clock for the in-package flash/PSRAM, powered by VDD_SPI and not for other use. |
| 34 | SPIQ | bidirectional | SPI data line (DO / SO / SIO1 / DQ1) for the in-package flash/PSRAM, powered by VDD_SPI and not for other use. |
| 35 | SPID | bidirectional | SPI data line (DI / SI / SIO0 / DQ0) for the in-package flash/PSRAM, powered by VDD_SPI and not for other use. |
| 36 | SPICLK_N | bidirectional | Negative differential SPI clock, powered by VDD_SPI or VDD3P3_CPU, reserved for in-package memory unless the chip is not connected to 8-line SPI memory. |
| 37 | SPICLK_P | bidirectional | Positive differential SPI clock, powered by VDD_SPI or VDD3P3_CPU, reserved for in-package memory unless the chip is not connected to 8-line SPI memory. |
| 38 | GPIO33 | bidirectional | Data line DQ4 for the in-package octal PSRAM/flash, powered by VDD_SPI or VDD3P3_CPU; usable as GPIO only if no 8-line SPI memory is connected. |
| 39 | GPIO34 | bidirectional | Data line DQ5 for the in-package octal PSRAM/flash, powered by VDD_SPI or VDD3P3_CPU; usable as GPIO only if no 8-line SPI memory is connected. |
| 40 | GPIO35 | bidirectional | Data line DQ6 for the in-package octal PSRAM/flash, powered by VDD_SPI or VDD3P3_CPU; usable as GPIO only if no 8-line SPI memory is connected. |
| 41 | GPIO36 | bidirectional | Data line DQ7 for the in-package octal PSRAM/flash, powered by VDD_SPI or VDD3P3_CPU; usable as GPIO only if no 8-line SPI memory is connected. |
| 42 | GPIO37 | bidirectional | Data strobe/data mask (DQS/DM) for the in-package octal memory, powered by VDD_SPI or VDD3P3_CPU; usable as GPIO only if no 8-line SPI memory is connected. |
| 43 | GPIO38 | bidirectional | General-purpose IO powered by VDD3P3_CPU, with FSPIWP and SUBSPIWP functions. |
| 44 | MTCK | bidirectional | JTAG test clock (default function), powered by VDD3P3_CPU; can be reassigned to GPIO39 via IO MUX. |
| 45 | MTDO | bidirectional | JTAG test data out (default function), powered by VDD3P3_CPU; can be reassigned to GPIO40 via IO MUX. |
| 46 | VDD3P3_CPU | power_in | Supply input for the digital power domain and digital IO pins. |
| 47 | MTDI | bidirectional | JTAG test data in (default function), powered by VDD3P3_CPU; can be reassigned to GPIO41 via IO MUX. |
| 48 | MTMS | bidirectional | JTAG test mode select (default function), powered by VDD3P3_CPU; can be reassigned to GPIO42 via IO MUX. |
| 49 | U0TXD | bidirectional | UART0 transmit (default function) with weak pull-up at reset, powered by VDD3P3_CPU; can be reassigned to GPIO43. |
| 50 | U0RXD | bidirectional | UART0 receive (default function) with weak pull-up at reset, powered by VDD3P3_CPU; can be reassigned to GPIO44. |
| 51 | GPIO45 | bidirectional | Strapping pin for VDD_SPI voltage selection, with weak pull-down at reset (default bit value 0). |
| 52 | GPIO46 | bidirectional | Strapping pin for chip boot mode and ROM message printing, with weak pull-down at reset (default bit value 0). |
| 53 | XTAL_N | passive | Negative external clock input/output connected to the chip's crystal or oscillator. |
| 54 | XTAL_P | passive | Positive external clock input/output connected to the chip's crystal or oscillator. |
| 55 | VDDA | power_in | Analog power domain supply input. |
| 56 | VDDA | power_in | Analog power domain supply input. |
| 57 | GND | power_in | External ground connection. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Espressif Systems |
| Package | 56-VFQFN Exposed Pad |
| Category | RF and Wireless |
| Pins | 57 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Allowed input voltage | -0.3 | 3.6 | V | 64 | |||
| Cumulative IO output current | Ioutput | 1500 | mA | 64 | |||
| Storage temperature | TSTORE | -40 | 150 | °C | 64 | ||
| Recommended input voltage | VDDA, VDD3P3 | 3 | 3.3 | 3.6 | V | 64 | |
| VDD_SPI (as input) | VDD_SPI | 1.8 | 3.3 | 3.6 | V | 64 | |
| Cumulative input current | IVDD | 0.5 | A | 64 | |||
| Input current high-level | IIH | 50 | nA | 65 | |||
| Input current low-level | IIL | 50 | nA | 65 | |||
| Differential nonlinearity | DNL | -4 | 4 | LSB | 66 | ||
| Integral nonlinearity | INL | -8 | 8 | LSB | 66 | ||
| Sampling rate | 100 | kSPS | 66 | ||||
| Total error | -5 | 5 | mV | ATTEN0, effective measurement range of 0 ~ 850 | 66 | ||
| Total error | -6 | 6 | mV | ATTEN1, effective measurement range of 0 ~ 1100 | 66 | ||
| Total error | -10 | 10 | mV | ATTEN2, effective measurement range of 0 ~ 1600 | 66 | ||
| Total error | -50 | 50 | mV | ATTEN3, effective measurement range of 0 ~ 2900 | 66 | ||
| Power supply voltage (1.8 V PSRAM) | VCC | 1.62 | 1.8 | 1.98 | V | 69 | |
| Power supply voltage (3.3 V PSRAM) | VCC | 2.7 | 3.3 | 3.6 | V | 69 | |
| Maximum clock frequency (PSRAM) | FC | 80 | MHz | 69 | |||
| Time reserved for power rails to stabilize before CHIP_PU is pulled high | tSTBL | 50 | µs | 30 | |||
| Time reserved for CHIP_PU to stay below VIL_nRST to reset the chip | tRST | 50 | µs | 30 | |||
| Pin capacitance | CIN | 2 | pF | 65 | |||
| High-level source current | IOH | 40 | mA | VDD = 3.3 V, VOH >= 2.64 V, PAD_DRIVER = 3 | 65 | ||
| Low-level sink current | IOL | 28 | mA | VDD = 3.3 V, VOL = 0.495 V, PAD_DRIVER = 3 | 65 | ||
| Internal weak pull-up resistor | RPU | 45 | kΩ | 65 | |||
| Internal weak pull-down resistor | RPD | 45 | kΩ | 65 | |||
| VDD_SPI powered by VDD3P3_RTC via RSPI for 3.3 V flash/PSRAM | RSPI | 14 | Ω | 65 | |||
| Output current when VDD_SPI is powered by Flash Voltage Regulator for 1.8 V flash/PSRAM | ISPI | 40 | mA | 65 |
CAD (KiCad official)
- Symbol:
ESP32-S3R2 - Footprint:
Package_DFN_QFN:QFN-56-1EP_7x7mm_P0.4mm_EP5.6x5.6mm - 3D model: 56-VFQFN Exposed Pad (KiCad packages3D, STEP)
- 3D model files:
esp32-s3r2-etched.step/esp32-s3r2-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);esp32-s3r2.step/esp32-s3r2.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Espressif Systems datasheet (87 pp, sha256
2d5a7cb7fd559d8d, retrieved 2026-10-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).