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ESP32-C3FN4

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Espressif Systems RF and Wireless, 32-VFQFN Exposed Pad. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ESP32-C3FN4

Espressif Systems · RF and Wireless · 32-VFQFN Exposed Pad

ESP32-C3FN4 from Espressif Systems, in a 32-VFQFN Exposed Pad. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 LNA_IN bidirectional RF low-noise amplifier (LNA) input/output signal pin.
2 VDD3P3 power_in Input power supply for the analog power domain.
3 VDD3P3 power_in Input power supply for the analog power domain.
4 XTAL_32K_P bidirectional Positive 32 kHz clock signal connected to the chip's crystal or oscillator; also usable as GPIO0 and ADC1_CH0.
5 XTAL_32K_N bidirectional Negative 32 kHz clock signal connected to the chip's crystal or oscillator; also usable as GPIO1 and ADC1_CH1.
6 GPIO2 bidirectional GPIO2 is a strapping pin that should be used with caution, with a default drive strength of 10 mA and ADC1_CH2 as an analog function.
7 CHIP_EN input High enables the chip (powered up) and low disables it (powered down); do not leave this pin floating.
8 GPIO3 bidirectional General-purpose IO with a default drive strength of 10 mA and ADC1_CH3 as an analog function.
9 MTMS bidirectional JTAG test mode select signal, with a default drive strength of 10 mA and ADC1_CH4 as an analog function.
10 MTDI bidirectional JTAG test data input, with a default drive strength of 10 mA and ADC2_CH0 as an analog function.
11 VDD3P3_RTC power_in Input power supply for the RTC and part of the digital power domains, powering the RTC IO pins.
12 MTCK bidirectional JTAG test clock signal; it has a low-level glitch of about 5 ns during power-up.
13 MTDO bidirectional JTAG test data output signal; it has a low-level glitch of about 5 ns during power-up.
14 GPIO8 bidirectional Strapping pin that should be used with caution because it is at a defined logic level at startup.
15 GPIO9 bidirectional Strapping pin with the internal weak pull-up enabled, which should be used with caution.
16 GPIO10 bidirectional General-purpose IO that is also usable as FSPICS0; it has a low-level glitch of about 5 ns during power-up.
17 VDD3P3_CPU power_in Input power supply for the digital power domain, powering the digital IO pins.
18 VDD_SPI power_in Input from the in-package flash backup power line and output supplying the in-package and off-package flash SPI IO; it can be reconfigured as a GPIO only if the flash has an external power supply.
19 SPIHD bidirectional SPI0/1 hold signal for the in-package flash, which is not recommended for other uses; the pin has the internal weak pull-up enabled.
20 SPIWP bidirectional SPI0/1 write-protect signal for the in-package flash, which is not recommended for other uses; the pin has the internal weak pull-up enabled.
21 SPICS0 bidirectional SPI0/1 chip-select signal for the in-package flash, which is not recommended for other uses; the pin has the internal weak pull-up enabled.
22 SPICLK bidirectional SPI0/1 clock signal for the in-package flash, which is not recommended for other uses; the pin has the internal weak pull-up enabled.
23 SPID bidirectional SPI0/1 data signal for the in-package flash, which is not recommended for other uses; the pin has the internal weak pull-up enabled.
24 SPIQ bidirectional SPI0/1 data signal for the in-package flash, which is not recommended for other uses; the pin has the internal weak pull-up enabled.
25 GPIO18 bidirectional General-purpose IO that is also the USB_D- signal of the USB Serial/JTAG controller; it has a high-level glitch of about 50000 ns during power-up and a default drive strength of 40 mA.
26 GPIO19 bidirectional General-purpose IO that is also the USB_D+ signal of the USB Serial/JTAG controller, with a default drive strength of 40 mA.
27 U0RXD bidirectional UART0 receive data signal with the internal weak pull-up enabled; it has a low-level glitch of about 5 ns during power-up.
28 U0TXD bidirectional UART0 transmit data signal with the internal weak pull-up enabled.
29 XTAL_N passive Differential external clock input/output negative connected to the chip's crystal or oscillator.
30 XTAL_P passive Differential external clock input/output positive connected to the chip's crystal or oscillator.
31 VDDA power_in Input power supply for the analog power domain.
32 VDDA power_in Input power supply for the analog power domain.
33 GND power_in Ground connection, given as the exposed pad of the QFN32 package.

Key specifications

Parameter Value
Manufacturer Espressif Systems
Package 32-VFQFN Exposed Pad
Category RF and Wireless
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input power pins allowed input voltage -0.3 3.6 V 54
Cumulative IO output current 1000 mA 54
Storage temperature -40 150 °C 54
Recommended input voltage (VDDA, VDD3P3, VDD3P3_RTC) 3 3.3 3.6 V 54
Recommended input voltage (VDD3P3_CPU) 3 3.3 3.6 V 54
Recommended input voltage (VDD_SPI as input) 3 3.3 3.6 V 54
Cumulative input current IV DD 0.5 A 54
Internal and output resistance, VDD_SPI powered by VDD3P3_CPU via RSPI RSPI 7.5 Ω VDD_SPI powered by VDD3P3_CPU via RSPI for 3.3 V flash 55
Pin capacitance CIN 2 pF 55
High-level input voltage (fraction of VDD) VIH 0.75 ×VDD 55
Low-level input voltage (fraction of VDD) VIL 0.25 ×VDD 55
High-level input current IIH 50 nA 55
Low-level input current IIL 50 nA 55
High-level output voltage (fraction of VDD) VOH 0.8 ×VDD 55
Low-level output voltage (fraction of VDD) VOL 0.1 ×VDD 55
High-level source current IOH 40 mA VDD = 3.3 V, VOH >= 2.64 V, PAD_DRIVER = 3 55
Low-level sink current IOL 28 mA VDD = 3.3 V, VOL = 0.495 V, PAD_DRIVER = 3 55
Internal weak pull-up resistor RPU 45 kΩ 55
Internal weak pull-down resistor RPD 45 kΩ 55
Chip reset release voltage (fraction of VDD) VIH_nRST 0.75 ×VDD CHIP_EN voltage is within the specified range 55
Chip reset voltage (fraction of VDD) VIL_nRST 0.25 ×VDD CHIP_EN voltage is within the specified range 55
Differential nonlinearity DNL -7 7 LSB ADC connected to an external 100 nF capacitor; DC signal input; ambient temperature at 25 °C; Wi-Fi off 56
Integral nonlinearity INL -12 12 LSB ADC connected to an external 100 nF capacitor; DC signal input; ambient temperature at 25 °C; Wi-Fi off 56
Sampling rate 100 kSPS 56
ADC total error ATTEN0 -10 10 mV effective measurement range of 0 ~ 750 56
ADC total error ATTEN1 -10 10 mV effective measurement range of 0 ~ 1050 56
ADC total error ATTEN2 -10 10 mV effective measurement range of 0 ~ 1300 56
ADC total error ATTEN3 -35 35 mV effective measurement range of 0 ~ 2500 56
Power supply voltage (1.8 V flash) VCC 1.65 1.8 2 V 57
Power supply voltage (3.3 V flash) VCC 2.7 3.3 3.6 V 57
Maximum clock frequency FC 80 MHz 57
Program/erase cycles 100000 cycles 57
Data retention time TRET 20 years 57
Page program time TPP 0.8 5 ms 57
Sector erase time (4 KB) TSE 70 500 ms 57
Block erase time (32 KB) TBE1 0.2 2 s 57
Block erase time (64 KB) TBE2 0.3 3 s 57
Chip erase time (16 Mb) TCE 7 20 s 57
Chip erase time (32 Mb) TCE 20 60 s 57
Chip erase time (64 Mb) TCE 25 100 s 57
Chip erase time (128 Mb) TCE 60 200 s 57
Chip erase time (256 Mb) TCE 70 300 s 58

CAD (KiCad official)

  • Symbol: ESP32-C3FN4
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.45x3.45mm
  • 3D model: 32-VFQFN Exposed Pad (KiCad packages3D, STEP)
  • 3D model files: esp32-c3fn4-etched.step / esp32-c3fn4-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); esp32-c3fn4.step / esp32-c3fn4.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Espressif Systems datasheet (76 pp, sha256 833fc000b4b3c3d3, retrieved 2026-10-27, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF