component
ESP32-C3FN4
Public Made by Adomby adom
Espressif Systems RF and Wireless, 32-VFQFN Exposed Pad. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.md+118docs/esp32-c3fn4-datasheet.pdfdocs/hero.pngesp32-c3fn4-etched.glbesp32-c3fn4-hero.glbesp32-c3fn4-hero.overlay.json+801esp32-c3fn4.glbesp32-c3fn4.kicad_mod+421esp32-c3fn4.kicad_sym+687esp32-c3fn4.lbr+208esp32-c3fn4.step+8354package.json+343page.json+349viewers/footprint.html+1viewers/symbol.html+1README.mdadded+118@@ -0,0 +1,118 @@+# ESP32-C3FN4++**Espressif Systems** · RF and Wireless · 32-VFQFN Exposed Pad++ESP32-C3FN4 from Espressif Systems, in a 32-VFQFN Exposed Pad. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | LNA_IN | bidirectional | RF low-noise amplifier (LNA) input/output signal pin. |+| 2 | VDD3P3 | power_in | Input power supply for the analog power domain. |+| 3 | VDD3P3 | power_in | Input power supply for the analog power domain. |+| 4 | XTAL_32K_P | bidirectional | Positive 32 kHz clock signal connected to the chip's crystal or oscillator; also usable as GPIO0 and ADC1_CH0. |+| 5 | XTAL_32K_N | bidirectional | Negative 32 kHz clock signal connected to the chip's crystal or oscillator; also usable as GPIO1 and ADC1_CH1. |+| 6 | GPIO2 | bidirectional | GPIO2 is a strapping pin that should be used with caution, with a default drive strength of 10 mA and ADC1_CH2 as an analog function. |+| 7 | CHIP_EN | input | High enables the chip (powered up) and low disables it (powered down); do not leave this pin floating. |+| 8 | GPIO3 | bidirectional | General-purpose IO with a default drive strength of 10 mA and ADC1_CH3 as an analog function. |+| 9 | MTMS | bidirectional | JTAG test mode select signal, with a default drive strength of 10 mA and ADC1_CH4 as an analog function. |+| 10 | MTDI | bidirectional | JTAG test data input, with a default drive strength of 10 mA and ADC2_CH0 as an analog function. |+| 11 | VDD3P3_RTC | power_in | Input power supply for the RTC and part of the digital power domains, powering the RTC IO pins. |+| 12 | MTCK | bidirectional | JTAG test clock signal; it has a low-level glitch of about 5 ns during power-up. |+| 13 | MTDO | bidirectional | JTAG test data output signal; it has a low-level glitch of about 5 ns during power-up. |+| 14 | GPIO8 | bidirectional | Strapping pin that should be used with caution because it is at a defined logic level at startup. |+| 15 | GPIO9 | bidirectional | Strapping pin with the internal weak pull-up enabled, which should be used with caution. |+| 16 | GPIO10 | bidirectional | General-purpose IO that is also usable as FSPICS0; it has a low-level glitch of about 5 ns during power-up. |+| 17 | VDD3P3_CPU | power_in | Input power supply for the digital power domain, powering the digital IO pins. |+| 18 | VDD_SPI | power_in | Input from the in-package flash backup power line and output supplying the in-package and off-package flash SPI IO; it can be reconfigured as a GPIO only if the flash has an external power supply. |+| 19 | SPIHD | bidirectional | SPI0/1 hold signal for the in-package flash, which is not recommended for other uses; the pin has the internal weak pull-up enabled. |+| 20 | SPIWP | bidirectional | SPI0/1 write-protect signal for the in-package flash, which is not recommended for other uses; the pin has the internal weak pull-up enabled. |+| 21 | SPICS0 | bidirectional | SPI0/1 chip-select signal for the in-package flash, which is not recommended for other uses; the pin has the internal weak pull-up enabled. |+| 22 | SPICLK | bidirectional | SPI0/1 clock signal for the in-package flash, which is not recommended for other uses; the pin has the internal weak pull-up enabled. |+| 23 | SPID | bidirectional | SPI0/1 data signal for the in-package flash, which is not recommended for other uses; the pin has the internal weak pull-up enabled. |+| 24 | SPIQ | bidirectional | SPI0/1 data signal for the in-package flash, which is not recommended for other uses; the pin has the internal weak pull-up enabled. |+| 25 | GPIO18 | bidirectional | General-purpose IO that is also the USB_D- signal of the USB Serial/JTAG controller; it has a high-level glitch of about 50000 ns during power-up and a default drive strength of 40 mA. |+| 26 | GPIO19 | bidirectional | General-purpose IO that is also the USB_D+ signal of the USB Serial/JTAG controller, with a default drive strength of 40 mA. |+| 27 | U0RXD | bidirectional | UART0 receive data signal with the internal weak pull-up enabled; it has a low-level glitch of about 5 ns during power-up. |+| 28 | U0TXD | bidirectional | UART0 transmit data signal with the internal weak pull-up enabled. |+| 29 | XTAL_N | passive | Differential external clock input/output negative connected to the chip's crystal or oscillator. |+| 30 | XTAL_P | passive | Differential external clock input/output positive connected to the chip's crystal or oscillator. |+| 31 | VDDA | power_in | Input power supply for the analog power domain. |+| 32 | VDDA | power_in | Input power supply for the analog power domain. |+| 33 | GND | power_in | Ground connection, given as the exposed pad of the QFN32 package. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Espressif Systems |+| Package | 32-VFQFN Exposed Pad |+| Category | RF and Wireless |+| Pins | 33 |++## Electrical characteristics++Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).++| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |+|---|---|---|---|---|---|---|---|+| Input power pins allowed input voltage | | -0.3 | | 3.6 | V | | 54 |+| Cumulative IO output current | | | | 1000 | mA | | 54 |+| Storage temperature | | -40 | | 150 | °C | | 54 |+| Recommended input voltage (VDDA, VDD3P3, VDD3P3_RTC) | | 3 | 3.3 | 3.6 | V | | 54 |+| Recommended input voltage (VDD3P3_CPU) | | 3 | 3.3 | 3.6 | V | | 54 |+| Recommended input voltage (VDD_SPI as input) | | 3 | 3.3 | 3.6 | V | | 54 |+| Cumulative input current | IV DD | 0.5 | | | A | | 54 |+| Internal and output resistance, VDD_SPI powered by VDD3P3_CPU via RSPI | RSPI | | 7.5 | | Ω | VDD_SPI powered by VDD3P3_CPU via RSPI for 3.3 V flash | 55 |+| Pin capacitance | CIN | | 2 | | pF | | 55 |+| High-level input voltage (fraction of VDD) | VIH | 0.75 | | | ×VDD | | 55 |+| Low-level input voltage (fraction of VDD) | VIL | | | 0.25 | ×VDD | | 55 |+| High-level input current | IIH | | | 50 | nA | | 55 |+| Low-level input current | IIL | | | 50 | nA | | 55 |+| High-level output voltage (fraction of VDD) | VOH | 0.8 | | | ×VDD | | 55 |+| Low-level output voltage (fraction of VDD) | VOL | | | 0.1 | ×VDD | | 55 |+| High-level source current | IOH | | 40 | | mA | VDD = 3.3 V, VOH >= 2.64 V, PAD_DRIVER = 3 | 55 |+| Low-level sink current | IOL | | 28 | | mA | VDD = 3.3 V, VOL = 0.495 V, PAD_DRIVER = 3 | 55 |+| Internal weak pull-up resistor | RPU | | 45 | | kΩ | | 55 |+| Internal weak pull-down resistor | RPD | | 45 | | kΩ | | 55 |+| Chip reset release voltage (fraction of VDD) | VIH_nRST | 0.75 | | | ×VDD | CHIP_EN voltage is within the specified range | 55 |+| Chip reset voltage (fraction of VDD) | VIL_nRST | | | 0.25 | ×VDD | CHIP_EN voltage is within the specified range | 55 |+| Differential nonlinearity | DNL | -7 | | 7 | LSB | ADC connected to an external 100 nF capacitor; DC signal input; ambient temperature at 25 °C; Wi-Fi off | 56 |+| Integral nonlinearity | INL | -12 | | 12 | LSB | ADC connected to an external 100 nF capacitor; DC signal input; ambient temperature at 25 °C; Wi-Fi off | 56 |+| Sampling rate | | | | 100 | kSPS | | 56 |+| ADC total error ATTEN0 | | -10 | | 10 | mV | effective measurement range of 0 ~ 750 | 56 |+| ADC total error ATTEN1 | | -10 | | 10 | mV | effective measurement range of 0 ~ 1050 | 56 |+| ADC total error ATTEN2 | | -10 | | 10 | mV | effective measurement range of 0 ~ 1300 | 56 |+| ADC total error ATTEN3 | | -35 | | 35 | mV | effective measurement range of 0 ~ 2500 | 56 |+| Power supply voltage (1.8 V flash) | VCC | 1.65 | 1.8 | 2 | V | | 57 |+| Power supply voltage (3.3 V flash) | VCC | 2.7 | 3.3 | 3.6 | V | | 57 |+| Maximum clock frequency | FC | 80 | | | MHz | | 57 |+| Program/erase cycles | | 100000 | | | cycles | | 57 |+| Data retention time | TRET | 20 | | | years | | 57 |+| Page program time | TPP | | 0.8 | 5 | ms | | 57 |+| Sector erase time (4 KB) | TSE | | 70 | 500 | ms | | 57 |+| Block erase time (32 KB) | TBE1 | | 0.2 | 2 | s | | 57 |+| Block erase time (64 KB) | TBE2 | | 0.3 | 3 | s | | 57 |+| Chip erase time (16 Mb) | TCE | | 7 | 20 | s | | 57 |+| Chip erase time (32 Mb) | TCE | | 20 | 60 | s | | 57 |+| Chip erase time (64 Mb) | TCE | | 25 | 100 | s | | 57 |+| Chip erase time (128 Mb) | TCE | | 60 | 200 | s | | 57 |+| Chip erase time (256 Mb) | TCE | | 70 | 300 | s | | 58 |++## CAD (KiCad official)++- Symbol: `ESP32-C3FN4`+- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.45x3.45mm`+- 3D model: 32-VFQFN Exposed Pad (KiCad packages3D, STEP)+- 3D model files: `esp32-c3fn4-etched.step` / `esp32-c3fn4-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `esp32-c3fn4.step` / `esp32-c3fn4.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Espressif Systems datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf) (76 pp, sha256 `833fc000b4b3c3d3`, retrieved 2026-10-27, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/esp32-c3fn4-datasheet.pdf)
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0.46,+ "orientation_flipped": false,+ "contacts_bbox_mm": [+ -2.5,+ 2.5,+ -2.5,+ 2.5+ ],+ "pads_bbox_mm": [+ -2.875,+ 2.875,+ -2.875,+ 2.875+ ],+ "seating_z_mm": 0.0+ },+ "sources": {+ "glb": "esp32-c3fn4-etched.glb",+ "glb_sha256": "cc174149136da30bbd431d6b6d5220597bb20dd8ad20845eac9bcb614365c6a1",+ "footprint": "esp32-c3fn4.kicad_mod",+ "footprint_sha256": "1d0e42ac74abb633e4811dd0533b5fe14b5e708feaa47b84ba2a4fb4521b6bc9",+ "pins": "page.json component.pins",+ "pins_sha256": "6f988f2efa33efee0bcf3bcd31eef5b6518fedd655db01069e3ab63e93526203"+ },+ "generator": "adom-wiki 1.8.0 (component_hero)",+ "labels": [+ {+ "pad": "1",+ "text": "LNA_IN",+ "x": -3.57,+ "y": -1.75,+ "align": "right",+ "vertical": false,+ "h": 0.25+ },+ {+ "pad": "2",+ "text": "VDD3P3",+ "x": -2.975,+ "y": -1.25,+ "align": "right",+ "vertical": false,+ "h": 0.25+ },+ {+ "pad": "3",+ "text": "VDD3P3",+ "x": -2.975,+ "y": -0.75,+ "align": "right",+ "vertical": false,+ "h": 0.25+ },+ {+ "pad": "4",+ "text": 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"number": "30",+ "shape": "roundrect",+ "center_mm": [+ -0.75,+ -2.4375+ ],+ "size_mm": [+ 0.25,+ 0.875+ ],+ "rot": 0.0+ },+ {+ "number": "31",+ "shape": "roundrect",+ "center_mm": [+ -1.25,+ -2.4375+ ],+ "size_mm": [+ 0.25,+ 0.875+ ],+ "rot": 0.0+ },+ {+ "number": "32",+ "shape": "roundrect",+ "center_mm": [+ -1.75,+ -2.4375+ ],+ "size_mm": [+ 0.25,+ 0.875+ ],+ "rot": 0.0+ },+ {+ "number": "33",+ "shape": "rect",+ "center_mm": [+ 0.0,+ 0.0+ ],+ "size_mm": [+ 3.45,+ 3.45+ ],+ "rot": 0.0+ }+ ]+}
esp32-c3fn4.glbadded⋯ 1 unchanged line ⋯
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esp32-c3fn4.kicad_symadded+687@@ -0,0 +1,687 @@+(kicad_symbol_lib+ (version 20251024)+ (generator "kicad_symbol_editor")+ (generator_version "10.0")+(symbol "ESP32-C3FN4"+ (exclude_from_sim no)+ (in_bom yes)+ (on_board yes)+ (in_pos_files yes)+ (duplicate_pin_numbers_are_jumpers no)+ (property "Reference" "U"+ (at -25.4 35.56 0)+ (show_name no)+ (do_not_autoplace no)+ (effects+ (font+ (size 1.27 1.27)+ )+ (justify left)+ )+ )+ (property "Value" "ESP32-C3FN4"+ (at -25.4 33.02 0)+ (show_name no)+ (do_not_autoplace no)+ (effects+ (font+ (size 1.27 1.27)+ )+ (justify left)+ )+ )+ (property "Footprint" "Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.45x3.45mm"+ (at 0 -38.1 0)+ (show_name no)+ (do_not_autoplace no)+ (hide yes)+ (effects+ (font+ (size 1.27 1.27)+ )+ )+ )+ (property "Datasheet" "https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf"+ (at 0 -40.64 0)+ (show_name no)+ (do_not_autoplace no)+ (hide yes)+ (effects+ (font+ (size 1.27 1.27)+ )+ )+ )+ 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length="middle" direction="pas"/>+ <pin name="VDDA@2" x="-38.1" y="2.5400000000000027" length="middle" direction="pas"/>+</symbol>+</symbols>+<devicesets>+<deviceset name="ESP32-C3FN4" prefix="U">+ <description>ESP32-C3 family is an ultra-low-power MCU-based SoC solution that supports 2.4 GHz Wi-Fi and Bluetooth®Low Energy (Bluetooth LE)</description>+ <gates>+ <gate name="G$1" symbol="ESP32-C3FN4" x="0" y="0"/>+ </gates>+ <devices>+ <device name="" package="QFN-32-1EP_5x5mm_P0.5mm_EP3.45x3.45mm">+ <connects>+ <connect gate="G$1" pin="LNA_IN" pad="1"/>+ <connect gate="G$1" pin="VDD3P3" pad="2"/>+ <connect gate="G$1" pin="XTAL_32K_P/ADC1_CH0" pad="4"/>+ <connect gate="G$1" pin="XTAL_32K_N/ADC1_CH1" pad="5"/>+ <connect gate="G$1" pin="GPIO2/ADC1_CH2" pad="6"/>+ <connect gate="G$1" pin="CHIP_EN" pad="7"/>+ <connect gate="G$1" pin="GPIO3/ADC1_CH3" pad="8"/>+ <connect gate="G$1" pin="MTMS/GPIO4/ADC1_CH4" pad="9"/>+ <connect gate="G$1" pin="MTDI/GPIO5/ADC2_CH0" pad="10"/>+ <connect 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esp32-c3fn4.stepadded+8354@@ -0,0 +1,8354 @@+ISO-10303-21; +HEADER; +/* QFN-32-1EP_5x5mm_Pitch0.5mm.step 3D STEP model for use in ECAD systems + * Copyright (C) 2017, kicad StepUp + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + * + * As a special exception, if you create a design which uses this symbol, + * and embed this symbol or unaltered portions of this symbol into the design, + * this symbol does not by itself cause the resulting design to be covered by + * the GNU General Public License. + * This exception does not however invalidate any other reasons why the design + * itself might be covered by the GNU General Public License. + * If you modify this symbol, you may extend this exception to your version of the symbol, + * but you are not obligated to do so. + * If you do not wish to do so, delete this exception statement from your version + * Risk disclaimer + * *USE 3D CAD DATA AT YOUR OWN RISK* + * *DO NOT RELY UPON ANY INFORMATION FOUND HERE WITHOUT INDEPENDENT VERIFICATION.* + * + */ + +FILE_DESCRIPTION( +/* description */ ('model of QFN-32-1EP_5x5mm_Pitch0.5mm'), +/* implementation_level */ '2;1'); + +FILE_NAME( +/* name */ 'QFN-32-1EP_5x5mm_Pitch0.5mm.step', +/* time_stamp */ '2017-03-23T11:16:46', +/* author */ ('kicad StepUp','ksu'), +/* organization */ ('FreeCAD'), +/* preprocessor_version */ 'OCC', +/* originating_system */ 'kicad StepUp', +/* authorisation */ ''); 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package.jsonadded+343@@ -0,0 +1,343 @@+{+ "slug": "esp32-c3fn4",+ "version": "0.1.0",+ "type": "component",+ "description": "Espressif Systems RF and Wireless, 32-VFQFN Exposed Pad. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "rf and wireless",+ "esp32-c3fn4",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "esp32-c3fn4.kicad_sym",+ "esp32-c3fn4.kicad_mod",+ "esp32-c3fn4.glb",+ "esp32-c3fn4.step",+ "esp32-c3fn4.lbr",+ "docs/hero.png",+ "docs/esp32-c3fn4-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "esp32-c3fn4-hero.glb",+ "esp32-c3fn4-hero.overlay.json",+ "esp32-c3fn4-etched.glb"+ ],+ "component": {+ "mpn": "ESP32-C3FN4",+ "manufacturer": "Espressif Systems",+ "package": "32-VFQFN Exposed Pad",+ "pin_count": 33,+ "category": "RF and Wireless",+ "subcategory": "RF and Wireless",+ "datasheet": "https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf",+ "parts": {+ "symbol": "esp32-c3fn4.kicad_sym",+ "footprint": "esp32-c3fn4.kicad_mod",+ "model_3d": "esp32-c3fn4-hero.glb",+ "model_3d_plain": "esp32-c3fn4-etched.glb",+ "model_3d_step": "esp32-c3fn4-etched.step",+ "model_3d_step_plain": "esp32-c3fn4.step",+ "lbr": "esp32-c3fn4.lbr"+ },+ "distributor_links": {+ "mouser": "356-ESP32-C3FN4"+ },+ "distributor_check": {+ "checked_at": "2026-10-27T23:33:52Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": null,+ "status": "deferred",+ "error": "shared DigiKey quota guard: 953 calls left today"+ },+ "mouser": {+ "pn": "356-ESP32-C3FN4",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "LNA_IN",+ "type": "bidirectional",+ "description": "RF low-noise amplifier (LNA) input/output signal pin."+ },+ {+ "number": "2",+ "name": "VDD3P3",+ "type": "power_in",+ "description": "Input power supply for the analog power domain."+ },+ {+ "number": "3",+ "name": "VDD3P3",+ "type": "power_in",+ "description": "Input power supply for the analog power domain."+ },+ {+ "number": "4",+ "name": "XTAL_32K_P",+ "type": "bidirectional",+ "description": "Positive 32 kHz clock signal connected to the chip's crystal or oscillator; also usable as GPIO0 and ADC1_CH0."+ },+ {+ "number": "5",+ "name": "XTAL_32K_N",+ "type": "bidirectional",+ "description": "Negative 32 kHz clock signal connected to the chip's crystal or oscillator; also usable as GPIO1 and ADC1_CH1."+ },+ {+ "number": "6",+ "name": "GPIO2",+ "type": "bidirectional",+ "description": "GPIO2 is a strapping pin that should be used with caution, with a default drive strength of 10 mA and ADC1_CH2 as an analog function."+ },+ {+ "number": "7",+ "name": "CHIP_EN",+ "type": "input",+ "description": "High enables the chip (powered up) and low disables it (powered down); do not leave this pin floating."+ },+ {+ "number": "8",+ "name": "GPIO3",+ "type": "bidirectional",+ "description": "General-purpose IO with a default drive strength of 10 mA and ADC1_CH3 as an analog function."+ },+ {+ "number": "9",+ "name": "MTMS",+ "type": "bidirectional",+ "description": "JTAG test mode select signal, with a default drive strength of 10 mA and ADC1_CH4 as an analog function."+ },+ {+ "number": "10",+ "name": "MTDI",+ "type": "bidirectional",+ "description": "JTAG test data input, with a default drive strength of 10 mA and ADC2_CH0 as an analog function."+ },+ {+ "number": "11",+ "name": "VDD3P3_RTC",+ "type": "power_in",+ "description": "Input power supply for the RTC and part of the digital power domains, powering the RTC IO pins."+ },+ {+ "number": "12",+ "name": "MTCK",+ "type": "bidirectional",+ "description": "JTAG test clock signal; it has a low-level glitch of about 5 ns during power-up."+ },+ {+ "number": "13",+ "name": "MTDO",+ "type": "bidirectional",+ "description": "JTAG test data output signal; it has a low-level glitch of about 5 ns during power-up."+ },+ {+ "number": "14",+ "name": "GPIO8",+ "type": "bidirectional",+ "description": "Strapping pin that should be used with caution because it is at a defined logic level at startup."+ },+ {+ "number": "15",+ "name": "GPIO9",+ "type": "bidirectional",+ "description": "Strapping pin with the internal weak pull-up enabled, which should be used with caution."+ },+ {+ "number": "16",+ "name": "GPIO10",+ "type": "bidirectional",+ "description": "General-purpose IO that is also usable as FSPICS0; it has a low-level glitch of about 5 ns during power-up."+ },+ {+ "number": "17",+ "name": "VDD3P3_CPU",+ "type": "power_in",+ "description": "Input power supply for the digital power domain, powering the digital IO pins."+ },+ {+ "number": "18",+ "name": "VDD_SPI",+ "type": "power_in",+ "description": "Input from the in-package flash backup power line and output supplying the in-package and off-package flash SPI IO; it can be reconfigured as a GPIO only if the flash has an external power supply."+ },+ {+ "number": "19",+ "name": "SPIHD",+ "type": "bidirectional",+ "description": "SPI0/1 hold signal for the in-package flash, which is not recommended for other uses; the pin has the internal weak pull-up enabled."+ },+ {+ "number": "20",+ "name": "SPIWP",+ "type": "bidirectional",+ "description": "SPI0/1 write-protect signal for the in-package flash, which is not recommended for other uses; the pin has the internal weak pull-up enabled."+ },+ {+ "number": "21",+ "name": "SPICS0",+ "type": "bidirectional",+ "description": "SPI0/1 chip-select signal for the in-package flash, which is not recommended for other uses; the pin has the internal weak pull-up enabled."+ },+ {+ "number": "22",+ "name": "SPICLK",+ "type": "bidirectional",+ "description": "SPI0/1 clock signal for the in-package flash, which is not recommended for other uses; the pin has the internal weak pull-up enabled."+ },+ {+ "number": "23",+ "name": "SPID",+ "type": "bidirectional",+ "description": "SPI0/1 data signal for the in-package flash, which is not recommended for other uses; the pin has the internal weak pull-up enabled."+ },+ {+ "number": "24",+ "name": "SPIQ",+ "type": "bidirectional",+ "description": "SPI0/1 data signal for the in-package flash, which is not recommended for other uses; the pin has the internal weak pull-up enabled."+ },+ {+ "number": "25",+ "name": "GPIO18",+ "type": "bidirectional",+ "description": "General-purpose IO that is also the USB_D- signal of the USB Serial/JTAG controller; it has a high-level glitch of about 50000 ns during power-up and a default drive strength of 40 mA."+ },+ {+ "number": "26",+ "name": "GPIO19",+ "type": "bidirectional",+ "description": "General-purpose IO that is also the USB_D+ signal of the USB Serial/JTAG controller, with a default drive strength of 40 mA."+ },+ {+ "number": "27",+ "name": "U0RXD",+ "type": "bidirectional",+ "description": "UART0 receive data signal with the internal weak pull-up enabled; it has a low-level glitch of about 5 ns during power-up."+ },+ {+ "number": "28",+ "name": "U0TXD",+ "type": "bidirectional",+ "description": "UART0 transmit data signal with the internal weak pull-up enabled."+ },+ {+ "number": "29",+ "name": "XTAL_N",+ "type": "passive",+ "description": "Differential external clock input/output negative connected to the chip's crystal or oscillator."+ },+ {+ "number": "30",+ "name": "XTAL_P",+ "type": "passive",+ "description": "Differential external clock input/output positive connected to the chip's crystal or oscillator."+ },+ {+ "number": "31",+ "name": "VDDA",+ "type": "power_in",+ "description": "Input power supply for the analog power domain."+ },+ {+ "number": "32",+ "name": "VDDA",+ "type": "power_in",+ "description": "Input power supply for the analog power domain."+ },+ {+ "number": "33",+ "name": "GND",+ "type": "power_in",+ "description": "Ground connection, given as the exposed pad of the QFN32 package."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The hint says 32-VFQFN Exposed Pad, but the datasheet calls the package QFN32 (5×5 mm). The pin list"+ ],+ "pages_sent": 38,+ "cost_usd": 0.1059,+ "at": "2026-10-27T23:34:15"+ },+ "datasheet": {+ "url": "https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf",+ "pages": 76,+ "sha256": "833fc000b4b3c3d3",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 33,+ "described": 33,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "esp32-c3fn4.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 5.0,+ 5.0,+ 0.77+ ],+ "zmin_mm": 0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "ba0561bc79f5a9da290aa7993318c1df3e9b747fb31b8816e75afc092c57352b",+ "checked": "2026-10-27",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "esp32-c3fn4-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 5.0,+ 5.0,+ 0.77+ ],+ "zmin_mm": 0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "f37128ad1f2f0c1cc4f3b46869d9ca409007c6bf8ef01d7b47de0892ccebdf9b",+ "checked": "2026-10-27",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ }+}
page.jsonadded+349@@ -0,0 +1,349 @@+{+ "slug": "esp32-c3fn4",+ "version": "0.1.0",+ "type": "component",+ "description": "Espressif Systems RF and Wireless, 32-VFQFN Exposed Pad. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "rf and wireless",+ "esp32-c3fn4",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "esp32-c3fn4.kicad_sym",+ "esp32-c3fn4.kicad_mod",+ "esp32-c3fn4.glb",+ "esp32-c3fn4.step",+ "esp32-c3fn4.lbr",+ "docs/hero.png",+ "docs/esp32-c3fn4-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "esp32-c3fn4-hero.glb",+ "esp32-c3fn4-hero.overlay.json",+ "esp32-c3fn4-etched.glb"+ ],+ "component": {+ "mpn": "ESP32-C3FN4",+ "manufacturer": "Espressif Systems",+ "package": "32-VFQFN Exposed Pad",+ "pin_count": 33,+ "category": "RF and Wireless",+ "subcategory": "RF and Wireless",+ "datasheet": "https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf",+ "parts": {+ "symbol": "esp32-c3fn4.kicad_sym",+ "footprint": "esp32-c3fn4.kicad_mod",+ "model_3d": "esp32-c3fn4-hero.glb",+ "model_3d_plain": "esp32-c3fn4-etched.glb",+ "model_3d_step": "esp32-c3fn4-etched.step",+ "model_3d_step_plain": "esp32-c3fn4.step",+ "lbr": "esp32-c3fn4.lbr"+ },+ "distributor_links": {+ "mouser": "356-ESP32-C3FN4"+ },+ "distributor_check": {+ "checked_at": "2026-10-27T23:33:52Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": null,+ "status": "deferred",+ "error": "shared DigiKey quota guard: 953 calls left today"+ },+ "mouser": {+ "pn": "356-ESP32-C3FN4",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "LNA_IN",+ "type": "bidirectional",+ "description": "RF low-noise amplifier (LNA) input/output signal pin."+ },+ {+ "number": "2",+ "name": "VDD3P3",+ "type": "power_in",+ "description": "Input power supply for the analog power domain."+ },+ {+ "number": "3",+ "name": "VDD3P3",+ "type": "power_in",+ "description": "Input power supply for the analog power domain."+ },+ {+ "number": "4",+ "name": "XTAL_32K_P",+ "type": "bidirectional",+ "description": "Positive 32 kHz clock signal connected to the chip's crystal or oscillator; also usable as GPIO0 and ADC1_CH0."+ },+ {+ "number": "5",+ "name": "XTAL_32K_N",+ "type": "bidirectional",+ "description": "Negative 32 kHz clock signal connected to the chip's crystal or oscillator; also usable as GPIO1 and ADC1_CH1."+ },+ {+ "number": "6",+ "name": "GPIO2",+ "type": "bidirectional",+ "description": "GPIO2 is a strapping pin that should be used with caution, with a default drive strength of 10 mA and ADC1_CH2 as an analog function."+ },+ {+ "number": "7",+ "name": "CHIP_EN",+ "type": "input",+ "description": "High enables the chip (powered up) and low disables it (powered down); do not leave this pin floating."+ },+ {+ "number": "8",+ "name": "GPIO3",+ "type": "bidirectional",+ "description": "General-purpose IO with a default drive strength of 10 mA and ADC1_CH3 as an analog function."+ },+ {+ "number": "9",+ "name": "MTMS",+ "type": "bidirectional",+ "description": "JTAG test mode select signal, with a default drive strength of 10 mA and ADC1_CH4 as an analog function."+ },+ {+ "number": "10",+ "name": "MTDI",+ "type": "bidirectional",+ "description": "JTAG test data input, with a default drive strength of 10 mA and ADC2_CH0 as an analog function."+ },+ {+ "number": "11",+ "name": "VDD3P3_RTC",+ "type": "power_in",+ "description": "Input power supply for the RTC and part of the digital power domains, powering the RTC IO pins."+ },+ {+ "number": "12",+ "name": "MTCK",+ "type": "bidirectional",+ "description": "JTAG test clock signal; it has a low-level glitch of about 5 ns during power-up."+ },+ {+ "number": "13",+ "name": "MTDO",+ "type": "bidirectional",+ "description": "JTAG test data output signal; it has a low-level glitch of about 5 ns during power-up."+ },+ {+ "number": "14",+ "name": "GPIO8",+ "type": "bidirectional",+ "description": "Strapping pin that should be used with caution because it is at a defined logic level at startup."+ },+ {+ "number": "15",+ "name": "GPIO9",+ "type": "bidirectional",+ "description": "Strapping pin with the internal weak pull-up enabled, which should be used with caution."+ },+ {+ "number": "16",+ "name": "GPIO10",+ "type": "bidirectional",+ "description": "General-purpose IO that is also usable as FSPICS0; it has a low-level glitch of about 5 ns during power-up."+ },+ {+ "number": "17",+ "name": "VDD3P3_CPU",+ "type": "power_in",+ "description": "Input power supply for the digital power domain, powering the digital IO pins."+ },+ {+ "number": "18",+ "name": "VDD_SPI",+ "type": "power_in",+ "description": "Input from the in-package flash backup power line and output supplying the in-package and off-package flash SPI IO; it can be reconfigured as a GPIO only if the flash has an external power supply."+ },+ {+ "number": "19",+ "name": "SPIHD",+ "type": "bidirectional",+ "description": "SPI0/1 hold signal for the in-package flash, which is not recommended for other uses; the pin has the internal weak pull-up enabled."+ },+ {+ "number": "20",+ "name": "SPIWP",+ "type": "bidirectional",+ "description": "SPI0/1 write-protect signal for the in-package flash, which is not recommended for other uses; the pin has the internal weak pull-up enabled."+ },+ {+ "number": "21",+ "name": "SPICS0",+ "type": "bidirectional",+ "description": "SPI0/1 chip-select signal for the in-package flash, which is not recommended for other uses; the pin has the internal weak pull-up enabled."+ },+ {+ "number": "22",+ "name": "SPICLK",+ "type": "bidirectional",+ "description": "SPI0/1 clock signal for the in-package flash, which is not recommended for other uses; the pin has the internal weak pull-up enabled."+ },+ {+ "number": "23",+ "name": "SPID",+ "type": "bidirectional",+ "description": "SPI0/1 data signal for the in-package flash, which is not recommended for other uses; the pin has the internal weak pull-up enabled."+ },+ {+ "number": "24",+ "name": "SPIQ",+ "type": "bidirectional",+ "description": "SPI0/1 data signal for the in-package flash, which is not recommended for other uses; the pin has the internal weak pull-up enabled."+ },+ {+ "number": "25",+ "name": "GPIO18",+ "type": "bidirectional",+ "description": "General-purpose IO that is also the USB_D- signal of the USB Serial/JTAG controller; it has a high-level glitch of about 50000 ns during power-up and a default drive strength of 40 mA."+ },+ {+ "number": "26",+ "name": "GPIO19",+ "type": "bidirectional",+ "description": "General-purpose IO that is also the USB_D+ signal of the USB Serial/JTAG controller, with a default drive strength of 40 mA."+ },+ {+ "number": "27",+ "name": "U0RXD",+ "type": "bidirectional",+ "description": "UART0 receive data signal with the internal weak pull-up enabled; it has a low-level glitch of about 5 ns during power-up."+ },+ {+ "number": "28",+ "name": "U0TXD",+ "type": "bidirectional",+ "description": "UART0 transmit data signal with the internal weak pull-up enabled."+ },+ {+ "number": "29",+ "name": "XTAL_N",+ "type": "passive",+ "description": "Differential external clock input/output negative connected to the chip's crystal or oscillator."+ },+ {+ "number": "30",+ "name": "XTAL_P",+ "type": "passive",+ "description": "Differential external clock input/output positive connected to the chip's crystal or oscillator."+ },+ {+ "number": "31",+ "name": "VDDA",+ "type": "power_in",+ "description": "Input power supply for the analog power domain."+ },+ {+ "number": "32",+ "name": "VDDA",+ "type": "power_in",+ "description": "Input power supply for the analog power domain."+ },+ {+ "number": "33",+ "name": "GND",+ "type": "power_in",+ "description": "Ground connection, given as the exposed pad of the QFN32 package."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The hint says 32-VFQFN Exposed Pad, but the datasheet calls the package QFN32 (5×5 mm). The pin list"+ ],+ "pages_sent": 38,+ "cost_usd": 0.1059,+ "at": "2026-10-27T23:34:15"+ },+ "datasheet": {+ "url": "https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf",+ "pages": 76,+ "sha256": "833fc000b4b3c3d3",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 33,+ "described": 33,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "esp32-c3fn4.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 5,+ 5,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "ba0561bc79f5a9da290aa7993318c1df3e9b747fb31b8816e75afc092c57352b",+ "checked": "2026-10-27",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "esp32-c3fn4-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 5,+ 5,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "f37128ad1f2f0c1cc4f3b46869d9ca409007c6bf8ef01d7b47de0892ccebdf9b",+ "checked": "2026-10-27",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}
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