component

EG1162

Public Made by Adom

by adom

EG Micro DC-DC Converters, SOP-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs eg1162: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers eg1162: viewers · Ray
eg1162-etched.fit.json eg1162: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
eg1162-etched.glb eg1162: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
eg1162-etched.step eg1162: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
eg1162.glb Publish 0.1.0 · Ray
eg1162.kicad_mod Publish 0.1.0 · Ray
eg1162.kicad_sym Publish 0.1.0 · Ray
eg1162.lbr Publish 0.1.0 · Ray
eg1162.step Publish 0.1.0 · Ray
package.json Publish 0.2.0 · Ray
page.json eg1162: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md eg1162: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray

EG1162

EG Micro · DC-DC Converters · SOP-16

EG1162 from EG Micro, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 REF3.3V power_out 3.3V internal reference output, maximum output current 50mA. Bypass with a small (e.g. 1uF) ceramic capacitor placed close to the pin.
2 EN input Chip enable pin. Comparator threshold 1.2V (typ). When EN < 1.2V, the chip enters standby and the 3.3V reference output is disabled. External resistor divider (R20/R21) sets the start/stop voltages.
3 SD input Shutdown input. Logic HIGH disables the PWM output; logic LOW enables PWM output. Threshold approximately 3V.
4 SS input Soft-start pin. Connect an external capacitor to GND; the capacitor's ramp rate determines the soft-start time.
5 VSS power_in Analog signal ground (AGND) for the chip.
6 CP input Oscillator timing capacitor pin. External capacitor Cp sets the PWM switching frequency: f = (18 x 10^6) / Cp (Cp in pF). Example: Cp = 270pF → ~67 kHz.
7 ERRO output Voltage-loop error amplifier output. Used for external loop compensation. Output current capability typ 20uA (15-25uA).
8 FB input Voltage-loop error amplifier inverting (negative) input. Internal reference 1.2V (typ). Set output voltage via divider: Vout = (1 + R1/R2) x 1.2V.
9 SDLIN input Low-side MOSFET current-sense comparator input. Trip threshold 180mV relative to COM (PGND). Used for cycle-by-cycle low-side current limit.
10 LO output Low-side gate driver output. Controls the turn-on/turn-off of the low-side (synchronous rectifier) power MOSFET. Source/sink capability ~1.8A/2A peak.
11 COM power_in Power ground (PGND) return for the low-side driver.
12 VCC power_in Low-side chip supply. Operating range 4.5V-20V (absolute max 20V). UVLO thresholds: ON = 4.6V, OFF = 3.8V. Requires a ~10uF storage capacitor to GND.
13 SDHIN input High-side MOSFET current-sense comparator input. Trip threshold 180mV relative to VS. Used for cycle-by-cycle high-side (peak) current limit.
14 VS output High-side floating ground / switch node reference. Connects to the source of the high-side MOSFET and the bootstrap capacitor's low side. Absolute rating VB-20 to VB+0.3V.
15 VB power_in High-side floating (bootstrap) supply. Typical operating range 4V to 600V referenced to VS. Bootstrap capacitor connects between VB and VS.
16 HO output High-side floating gate driver output. Controls the turn-on/turn-off of the high-side power MOSFET, swinging between VS and VB. Source/sink capability ~1.8A/2A peak.

Key specifications

Parameter Value
Manufacturer EG Micro
Package SOP-16
Category PMIC
Pins 16

CAD (KiCad official)

  • Symbol: EG1162
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: eg1162-etched.step / eg1162-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); eg1162.step / eg1162.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
eg1162.step 217 KB You want the bare part, or you mark your own boards.
eg1162-etched.step 1.8 MB You want the part with EG1162 already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 458 faces against 267 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: EG Micro datasheet (13 pp, sha256 5379721bee5f9bbb, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF