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EFM8BB22F16I-C-QFN28

Public Made by Adom

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SILICON LABS Pre-ordered MCUs, VQFN-28-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersefm8bb22f16i-c-qfn28factory-2.0.0extractor-text

Verified EFM8BB22F16I-C-QFN28

by Ray · last 8 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

8 Nov 2026RayPublished by the parts factory: tier lcsc, 29 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: EFM8BB22F16I-C-QFN28 · VQFN-28-EP(5x5) · 29 pins
  • ✓copper: 29 copper pads, none touching another net
  • ✓datasheet: all 29 pin names found in the 59-page datasheet
  • ✓distributor: lcsc C1340864, digikey 336-3642-5-ND, mouser 634-8BB22F16ICQFN28
  • ✓family: QFN-28-1EP_5x5mm_P0.5mm_EP3.35x3.35mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-zc4gb3x8/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 29 pins = 29 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 29 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ efm8bb22f16i-c-qfn28.kicad_sym✓ efm8bb22f16i-c-qfn28.kicad_mod✓ efm8bb22f16i-c-qfn28.step
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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

markdown

EFM8BB22F16I-C-QFN28

SILICON LABS · Pre-ordered MCUs · VQFN-28-EP(5x5)

EFM8BB22F16I-C-QFN28 from SILICON LABS, in a VQFN-28-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P0.1 bidirectional Multifunction I/O with crossbar capability, P0MAT.1, INT0.1/INT1.1, ADC0.1, CMP0P.1/CMP0N.1 and AGND analog function.
2 P0.0 bidirectional Multifunction I/O with crossbar capability, P0MAT.0, INT0.0/INT1.0, ADC0.0, CMP0P.0/CMP0N.0 and VREF analog function.
3 GND power_in Ground.
4 N/C unconnected No connection.
5 N/C unconnected No connection.
6 VDD power_in Supply power input / 5V regulator output.
7 VREGIN power_in 5V regulator input.
8 P3.1 bidirectional Multifunction I/O (no crossbar capability listed).
9 RSTb / C2CK bidirectional Active-low reset / C2 debug clock.
10 P3.0 / C2D bidirectional Multifunction I/O / C2 debug data.
11 P2.3 bidirectional Multifunction I/O with crossbar capability, P2MAT.3, ADC0.23, CP1P.12/CP1N.12.
12 P2.2 bidirectional Multifunction I/O with crossbar capability, P2MAT.2, ADC0.22, CP1P.11/CP1N.11.
13 P2.1 bidirectional Multifunction I/O with crossbar capability, P2MAT.1, ADC0.21, CP1P.10/CP1N.10.
14 P2.0 bidirectional Multifunction I/O with crossbar capability, P2MAT.0, ADC0.20, CP1P.9/CP1N.9.
15 P1.7 bidirectional Multifunction I/O with crossbar capability, P1MAT.7, ADC0.15, CP1P.7/CP1N.7.
16 P1.6 bidirectional Multifunction I/O with crossbar capability, P1MAT.6, I2C0_SCL, ADC0.14, CP1P.6/CP1N.6.
17 P1.5 bidirectional Multifunction I/O with crossbar capability, P1MAT.5, I2C0_SDA, ADC0.13, CP1P.5/CP1N.5.
18 P1.4 bidirectional Multifunction I/O with crossbar capability, P1MAT.4, ADC0.12, CP1P.4/CP1N.4.
19 P1.3 bidirectional Multifunction I/O with crossbar capability, P1MAT.3, ADC0.11, CP1P.3/CP1N.3.
20 P1.2 bidirectional Multifunction I/O with crossbar capability, P1MAT.2, ADC0.10, CP1P.2/CP1N.2.
21 P1.1 bidirectional Multifunction I/O with crossbar capability, P1MAT.1, ADC0.9, CP1P.1/CP1N.1, CMP0P.10/CMP0N.10.
22 P1.0 bidirectional Multifunction I/O with crossbar capability, P1MAT.0, ADC0.8, CP1P.0/CP1N.0, CMP0P.9/CMP0N.9.
23 P0.7 bidirectional Multifunction I/O with crossbar capability, P0MAT.7, INT0.7/INT1.7, ADC0.7, CMP0P.7/CMP0N.7.
24 P0.6 bidirectional Multifunction I/O with crossbar capability, P0MAT.6, CNVSTR, INT0.6/INT1.6, ADC0.6, CMP0P.6/CMP0N.6.
25 P0.5 bidirectional Multifunction I/O with crossbar capability, P0MAT.5, INT0.5/INT1.5, UART0_RX, ADC0.5, CMP0P.5/CMP0N.5.
26 P0.4 bidirectional Multifunction I/O with crossbar capability, P0MAT.4, INT0.4/INT1.4, UART0_TX, ADC0.4, CMP0P.4/CMP0N.4.
27 P0.3 bidirectional Multifunction I/O with crossbar capability, P0MAT.3, EXTCLK, INT0.3/INT1.3, ADC0.3, CMP0P.3/CMP0N.3.
28 P0.2 bidirectional Multifunction I/O with crossbar capability, P0MAT.2, INT0.2/INT1.2, ADC0.2, CMP0P.2/CMP0N.2.
29 GND power_in Center exposed pad, ground.

Key specifications

Parameter Value
Manufacturer SILICON LABS
Package VQFN-28-EP(5x5)
Category Embedded Processors & Controllers
Pins 29

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating Supply Voltage on VDD VDD 2.2 3.6 V 16
Operating Supply Voltage on VREGIN VREGIN 3 5.25 V 16
System Clock Frequency fSYSCLK 0 50 MHz 16
Operating Ambient Temperature TA -40 125 °C I-grade or A-grade devices 16
Digital Core Supply Current, Normal Mode IDD 9.4 10.9 mA I-grade/A-grade; FSYSCLK = 49 MHz (HFOSC1) 17
Digital Core Supply Current, Normal Mode IDD 4.5 5.6 mA I-grade/A-grade; FSYSCLK = 24.5 MHz (HFOSC0) 17
Digital Core Supply Current, Normal Mode IDD 600 1555 μA I-grade/A-grade; FSYSCLK = 1.53 MHz (HFOSC0) 17
Digital Core Supply Current, Normal Mode IDD 145 1070 μA I-grade/A-grade; FSYSCLK = 80 kHz 17
Digital Core Supply Current, Idle Mode IDD 6.3 7.4 mA I-grade/A-grade; FSYSCLK = 49 MHz (HFOSC1) 17
Digital Core Supply Current, Idle Mode IDD 2.9 3.9 mA I-grade/A-grade; FSYSCLK = 24.5 MHz (HFOSC0) 17
Digital Core Supply Current, Idle Mode IDD 440 1400 μA I-grade/A-grade; FSYSCLK = 1.53 MHz (HFOSC0) 17
Digital Core Supply Current, Idle Mode IDD 130 1050 μA I-grade/A-grade; FSYSCLK = 80 kHz 17
Digital Core Supply Current, Suspend Mode IDD 125 1050 μA I-grade/A-grade; LFO Running 17
Digital Core Supply Current, Suspend Mode IDD 120 1045 μA I-grade/A-grade; LFO Stopped 17
Digital Core Supply Current, Snooze Mode IDD 25 950 μA I-grade/A-grade; LFO Running 18
Digital Core Supply Current, Snooze Mode IDD 20 940 μA I-grade/A-grade; LFO Stopped 18
Digital Core Supply Current, Stop Mode IDD 120 1045 μA I-grade/A-grade; Internal LDO On 18
Digital Core Supply Current, Shutdown Mode IDD 0.2 15 μA I-grade/A-grade; Internal LDO Off 18
High-Frequency Oscillator 1 Supply Current IHFOSC1 865 940 μA Operating at 49 MHz, TA = 25 °C 18
ADC0 Always-on Supply Current IADC 820 1200 μA 800 ksps 10-bit or 200 ksps 12-bit conversions; Normal bias settings; VDD = 3.0 V 18
ADC0 Always-on Supply Current IADC 405 580 μA 250 ksps 10-bit or 62.5 ksps 12-bit conversions; Low power bias settings; VDD = 3.0 V 18
Internal ADC0 Reference Supply Current, Normal Power Mode IVREFFS 680 790 μA Normal Power Mode 19
Internal ADC0 Reference Supply Current, Low Power Mode IVREFFS 160 210 μA Low Power Mode 19
Temperature Sensor Supply Current ITSENSE 70 120 μA 19
Voltage Supply Monitor Supply Current IVMON 15 20 μA 19
5V Regulator Supply Current, Normal Mode IVREG 245 340 μA SUSEN = 0, BIASENB = 0 19
5V Regulator Supply Current, Suspend Mode IVREG 60 100 μA SUSEN = 1, BIASENB = 0 19
5V Regulator Supply Current, Bias Disabled IVREG 2.5 10 μA BIASENB = 1 19
VDD Supply Monitor Threshold VVDDM 1.95 2.05 2.15 V 20
Falling Voltage on VDD (POR Threshold) VPOR 0.75 1.36 V Falling Voltage on VDD 20
Reset Delay from POR tPOR 3 10 31 ms Relative to VDD > VPOR 20
RST Low Time to Generate Reset tRSTL 15 μs 20
Missing Clock Detector Response Time (final rising edge to reset) tMCD 0.625 1.2 ms FSYSCLK > 1 MHz 20
Missing Clock Detector Trigger Frequency FMCD 7.5 13.5 kHz 20
Write Time tWRITE 19 20 21 μs One Byte, FSYSCLK = 24.5 MHz 20
Erase Time tERASE 5.2 5.35 5.5 ms One Page, FSYSCLK = 24.5 MHz 20
VDD Voltage During Programming VPROG 2.2 3.6 V 20
Idle Mode Wake-up Time tIDLEWK 2 3 SYSCLKs 21
High Frequency Oscillator 0 Frequency fHFOSC0 24 24.5 25 MHz Full Temperature and Supply Range 21
High Frequency Oscillator 1 Frequency fHFOSC1 48.25 49 49.75 MHz Full Temperature and Supply Range 21
Low Frequency Oscillator Frequency fLFOSC 75 80 85 kHz Full Temperature and Supply Range 21
Internal Fast Settling Reference Output Voltage VREFFS 1.62 1.65 1.68 V 1.65 V Setting, Full Temperature and Supply Range 24
Internal Fast Settling Reference Output Voltage VREFFS 2.35 2.4 2.45 V 2.4 V Setting, VDD > 2.6 V 24
1.8 V Internal LDO Output Voltage VOUT_1.8V 1.78 1.85 1.92 V 25
Output Voltage on VDD (5V Regulator) VREGOUT 3.1 3.3 3.6 V Output Current = 1 to 100 mA; Regulation range (VREGIN ≥ 4.1 V) 25
Output Current (5V Regulator) IREGOUT 100 mA 25
Dropout Voltage (5V Regulator) VDROPOUT 0.8 V Output Current = 100 mA 25
Ambient Temperature Under Bias TBIAS -55 125 °C 28
Storage Temperature TSTG -65 150 °C 28
Voltage on VDD VDD 4.2 V 28
Voltage on VREGIN VREGIN 5.8 V 28
Voltage on I/O pins or RSTb VIN 5.8 V VDD > 3.3 V 28
Total Current Sunk into Supply Pin IVDD 200 mA 28
Total Current Sourced out of Ground Pin IGND 200 mA 28
Current Sourced or Sunk by any I/O Pin or RSTb IIO -100 100 mA 28
Operating Junction Temperature TJ -40 130 °C TA = -40 °C to 125 °C (I-grade or A-grade parts only) 28
Output Low Voltage (High Drive) VOL 0.6 V IOL = 13.5 mA, VDD ≥ 3.0 V 27
Input Low Voltage VIL 0.6 V 27
Weak Pull-Up Current IPU -30 -20 -10 μA VIN = 0 V, VDD = 3.6 27
Thermal Resistance (Junction to Ambient) θJA 26 °C/W QFN-28 Packages 27

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 46

CAD (KiCad official)

  • Symbol: EFM8BB22F16I-C-QFN28
  • Footprint: Package_DFN_QFN:QFN-28-1EP_5x5mm_P0.5mm_EP3.35x3.35mm
  • 3D model: VQFN-28-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: efm8bb22f16i-c-qfn28-etched.step / efm8bb22f16i-c-qfn28-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); efm8bb22f16i-c-qfn28.step / efm8bb22f16i-c-qfn28.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SILICON LABS datasheet (59 pp, sha256 68db19b3e729b537, retrieved 2026-11-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF