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EFM32TG11B520F128GQ80-B

Public Made by Adom

by adom

SILICON LABS SILICON LABS, TQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersefm32tg11b520f128gq80-bfactory-2.0.0extractor-text
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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

markdown

EFM32TG11B520F128GQ80-B

SILICON LABS · SILICON LABS · TQFP-80(12x12)

EFM32TG11B520F128GQ80-B from SILICON LABS, in a TQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA0 bidirectional GPIO with LCD_SEG13, TIM0_CC0, I2C0_SDA, GPIO_EM4WU0 and other alternate functions.
2 PA1 bidirectional GPIO with LCD_SEG14, TIM0_CC1, I2C0_SCL, CMU_CLK1 and other alternate functions.
3 PA2 bidirectional GPIO with LCD_SEG15, TIM0_CC2, US3_CLK, CMU_CLK0 and other alternate functions.
4 PA3 bidirectional GPIO with LCD_SEG16, TIM0_CDTI0, US3_CS, LES_ALTEX2 and other alternate functions.
5 PA4 bidirectional GPIO with LCD_SEG17, TIM0_CDTI1, US3_CTS, LES_ALTEX3 and other alternate functions.
6 PA5 bidirectional GPIO with LCD_SEG18, TIM0_CDTI2, US3_RTS, LES_ALTEX4 and other alternate functions.
7 PA6 bidirectional GPIO with LCD_SEG19, WTIM0_CC0, PRS_CH6, GPIO_EM4WU1 and other alternate functions.
8 IOVDD0 power_in Digital IO power supply 0.
9 VSS power_in Ground.
10 PB3 bidirectional GPIO with LCD_SEG20/LCD_COM4, TIM1_CC3, US2_TX and other alternate functions.
11 PB4 bidirectional GPIO with LCD_SEG21/LCD_COM5, WTIM0_CC1, US2_RX and other alternate functions.
12 PB5 bidirectional GPIO with LCD_SEG22/LCD_COM6, WTIM0_CC2, US2_CLK and other alternate functions.
13 PB6 bidirectional GPIO with LCD_SEG23/LCD_COM7, TIM0_CC0, US2_CS and other alternate functions.
14 PC1 bidirectional GPIO, 5V tolerant, with CAN0_TX, LES_CH1, OPA0_OUTALT and other alternate functions.
15 PC2 bidirectional GPIO, 5V tolerant, with LES_CH2, OPA0_OUTALT, US2_TX and other alternate functions.
16 PC3 bidirectional GPIO, 5V tolerant, with LES_CH3, OPA0_OUTALT, US2_RX and other alternate functions.
17 PC4 bidirectional GPIO with OPA0_P, LCD_SEG24, LES_CH4, GPIO_EM4WU6 and other alternate functions.
18 PC5 bidirectional GPIO with OPA0_N, LCD_SEG25, LES_CH5 and other alternate functions.
19 PB7 bidirectional GPIO with LFXTAL_P (low frequency crystal positive pin) and other alternate functions.
20 PB8 bidirectional GPIO with LFXTAL_N (low frequency crystal negative pin or external clock input) and other alternate functions.
21 PA8 bidirectional GPIO with BU_STAT (backup power domain status), TIM0_CC0, US2_RX and other alternate functions.
22 PA9 bidirectional GPIO with LCD_SEG26, TIM0_CC1, US2_CLK and other alternate functions.
23 PA10 bidirectional GPIO with LCD_SEG27, TIM0_CC2, US2_CS and other alternate functions.
24 VSS power_in Ground.
25 PA12 bidirectional GPIO with BU_VOUT (backup domain power output), WTIM0_CDTI0, US0_CLK and other alternate functions.
26 PA14 bidirectional GPIO with LCD_BEXT, WTIM0_CDTI2, US1_TX and other alternate functions.
27 RESETn input Reset input, active low; drive low only during reset and let the internal pull-up release reset.
28 PB11 bidirectional GPIO with VDAC0_OUT0/OPA0_OUT, LCD_SEG28, GPIO_EM4WU7 and other alternate functions.
29 PB12 bidirectional GPIO with VDAC0_OUT1/OPA1_OUT, LCD_SEG29, I2C1_SCL and other alternate functions.
30 AVDD power_in Analog power supply.
31 PB13 bidirectional GPIO with HFXTAL_P (high frequency crystal positive pin), WTIM1_CC0 and other alternate functions.
32 PB14 bidirectional GPIO with HFXTAL_N (high frequency crystal negative pin or external clock input), WTIM1_CC1 and other alternate functions.
33 IOVDD0 power_in Digital IO power supply 0.
34 AVDD power_in Analog power supply.
35 PD0 bidirectional GPIO, 5V tolerant, with OPA2_OUTALT, VDAC0_OUT0ALT/OPA0_OUTALT, CAN0_RX and other alternate functions.
36 PD1 bidirectional GPIO with OPA3_OUT, VDAC0_OUT1ALT/OPA1_OUTALT, CAN0_TX and other alternate functions.
37 PD3 bidirectional GPIO with OPA2_N, LCD_SEG30, TIM0_CC2 and other alternate functions.
38 PD4 bidirectional GPIO with OPA2_P, LCD_SEG31, LEU0_TX and other alternate functions.
39 PD5 bidirectional GPIO with OPA2_OUT, LEU0_RX, I2C1_SCL and other alternate functions.
40 PD6 bidirectional GPIO with ADC0_EXTP, VDAC0_EXT, OPA1_P, I2C0_SDA and other alternate functions.
41 PD7 bidirectional GPIO with ADC0_EXTN, OPA1_N, I2C0_SCL and other alternate functions.
42 PD8 bidirectional GPIO with BU_VIN (battery input for backup power domain), WTIM1_CC2 and other alternate functions.
43 PC6 bidirectional GPIO with OPA3_P, LCD_SEG32, LES_CH6 and other alternate functions.
44 PC7 bidirectional GPIO with OPA3_N, LCD_SEG33, LES_CH7 and other alternate functions.
45 VREGVSS power_in Voltage regulator VSS.
46 VREGSW passive DCDC regulator switching node.
47 VREGVDD power_in Voltage regulator VDD input.
48 DVDD power_in Digital power supply.
49 DECOUPLE passive Decouple output for on-chip voltage regulator; an external decoupling capacitor is required at this pin.
50 IOVDD0 power_in Digital IO power supply 0.
51 VSS power_in Ground.
52 PE4 bidirectional GPIO with LCD_COM0, WTIM0_CC0, US0_CS and other alternate functions.
53 PE5 bidirectional GPIO with LCD_COM1, WTIM0_CC1, US0_CLK and other alternate functions.
54 PE6 bidirectional GPIO with LCD_COM2, WTIM0_CC2, US0_RX and other alternate functions.
55 PE7 bidirectional GPIO with LCD_COM3, WTIM1_CC0, US0_TX and other alternate functions.
56 PC8 bidirectional GPIO with LCD_SEG34, LES_CH8, US0_CS and other alternate functions.
57 PC9 bidirectional GPIO with LCD_SEG35, LES_CH9, GPIO_EM4WU2 and other alternate functions.
58 PC10 bidirectional GPIO, 5V tolerant, with LES_CH10, US0_RX and other alternate functions.
59 PC11 bidirectional GPIO, 5V tolerant, with LES_CH11, US0_TX, I2C1_SDA and other alternate functions.
60 PC13 bidirectional GPIO, 5V tolerant, with LES_CH13, TIM1_CC0, PCNT0_S0IN and other alternate functions.
61 PC14 bidirectional GPIO, 5V tolerant, with LES_CH14, TIM1_CC1, PCNT0_S1IN and other alternate functions.
62 PC15 bidirectional GPIO, 5V tolerant, with LES_CH15, TIM1_CC2, LEU0_RX and other alternate functions.
63 PF0 bidirectional GPIO, 5V tolerant, with DBG_SWCLKTCK (debug clock, built-in pull down out of reset), BOOT_TX and other alternate functions.
64 PF1 bidirectional GPIO, 5V tolerant, with DBG_SWDIOTMS (debug data, built-in pull up out of reset), BOOT_RX, GPIO_EM4WU3 and other alternate functions.
65 PF2 bidirectional GPIO with LCD_SEG0, DBG_TDO, GPIO_EM4WU4 and other alternate functions.
66 PF3 bidirectional GPIO with LCD_SEG1, TIM0_CDTI0, TIM1_CC1 and other alternate functions.
67 PF4 bidirectional GPIO with LCD_SEG2, TIM0_CDTI1, TIM1_CC2 and other alternate functions.
68 PF5 bidirectional GPIO with LCD_SEG3, DBG_TDI, TIM0_CDTI2 and other alternate functions.
69 IOVDD0 power_in Digital IO power supply 0.
70 VSS power_in Ground.
71 PE8 bidirectional GPIO with LCD_SEG4, PRS_CH3 and other alternate functions.
72 PE9 bidirectional GPIO with LCD_SEG5 and other alternate functions.
73 PE10 bidirectional GPIO with LCD_SEG6, TIM1_CC0, US0_TX, GPIO_EM4WU9 and other alternate functions.
74 PE11 bidirectional GPIO with LCD_SEG7, TIM1_CC1, US0_RX, LES_ALTEX5 and other alternate functions.
75 BODEN input Brown-Out Detector Enable; may be left disconnected or tied to AVDD.
76 PE12 bidirectional GPIO with LCD_SEG8, TIM1_CC2, US0_CLK, I2C0_SDA and other alternate functions.
77 PE13 bidirectional GPIO with LCD_SEG9, TIM1_CC3, US0_CS, GPIO_EM4WU5 and other alternate functions.
78 PE14 bidirectional GPIO with LCD_SEG10, US0_CTS, LEU0_TX and other alternate functions.
79 PE15 bidirectional GPIO with LCD_SEG11, US0_RTS, LEU0_RX and other alternate functions.
80 PA15 bidirectional GPIO with LCD_SEG12, US2_CLK and other alternate functions.

Key specifications

Parameter Value
Manufacturer SILICON LABS
Package TQFP-80(12x12)
Category Embedded Processors & Controllers
Pins 80

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage temperature range TSTG -50 150 °C 19
Voltage on any supply pin VDDMAX -0.3 3.8 V 19
Voltage ramp rate on any supply pin VDDRAMPMAX 1 V / µs 19
Total current into VDD power lines IVDDMAX 200 mA Source 19
Total current into VSS ground lines IVSSMAX 200 mA Sink 19
Current per I/O pin IIOMAX 50 mA Sink 19
Current for all I/O pins IIOALLMAX 200 mA Sink 19
Junction temperature TJ -40 105 °C -G grade devices 19
Operating ambient temperature range TA -40 25 85 °C -G temperature grade 21
AVDD supply voltage VAVDD 1.8 3.3 3.8 V 21
VREGVDD operating supply voltage VVREGVDD 2.4 3.3 3.8 V DCDC in regulation 21
VREGVDD operating supply voltage VVREGVDD 1.8 3.3 3.8 V DCDC in bypass, 50mA load 21
VREGVDD current IVREGVDD 200 mA DCDC in bypass, T ≤ 85 °C 21
VREGVDD current IVREGVDD 100 mA DCDC in bypass, T > 85 °C 21
DVDD operating supply voltage VDVDD 1.62 V 21
IOVDD operating supply voltage VIOVDD 1.62 V All IOVDD pins 21
DECOUPLE output capacitor CDECOUPLE 0.75 1 2.75 µF 21
HFCORECLK frequency fCORE 48 MHz VSCALE2, MODE = WS1 21
HFCORECLK frequency fCORE 25 MHz VSCALE2, MODE = WS0 21
HFCORECLK frequency fCORE 20 MHz VSCALE0, MODE = WS1 21
HFCORECLK frequency fCORE 10 MHz VSCALE0, MODE = WS0 21
HFCLK frequency fHFCLK 48 MHz VSCALE2 21
HFCLK frequency fHFCLK 20 MHz VSCALE0 21
Thermal resistance, TQFP80 Package THETAJA_TQFP80 49.3 °C/W 4-Layer PCB, Air velocity = 0 m/s 22
Thermal resistance, TQFP80 Package THETAJA_TQFP80 44.5 °C/W 4-Layer PCB, Air velocity = 1 m/s 22
Thermal resistance, TQFP80 Package THETAJA_TQFP80 42.6 °C/W 4-Layer PCB, Air velocity = 2 m/s 22
DC-DC input voltage range VDCDC_I 1.8 V Bypass mode, IDCDC_LOAD = 50 mA 23
DC-DC input voltage range VDCDC_I 2.4 V Low noise (LN) mode, 1.8 V output, IDCDC_LOAD = 100 mA, or Low power (LP) mode, 1.8 V output, IDCDC_LOAD = 10 mA 23
DC-DC input voltage range VDCDC_I 2.6 V Low noise (LN) mode, 1.8 V output, IDCDC_LOAD = 200 mA 23
Regulation DC accuracy ACCDC 1.7 1.9 V Low Noise (LN) mode, 1.8 V target output 23
Regulation window WINREG 1.63 2.2 V Low Power (LP) mode, LPCMPBIASEMxx = 0, 1.8 V target output, IDCDC_LOAD ≤ 75 µA 23
Regulation window WINREG 1.63 2.1 V Low Power (LP) mode, LPCMPBIASEMxx = 3, 1.8 V target output, IDCDC_LOAD ≤ 10 mA 23
Output voltage under/overshoot VOV 25 60 mV CCM Mode (LNFORCECCM = 1), Load changes between 0 mA and 100 mA 23
Output voltage under/overshoot VOV 45 90 mV DCM Mode (LNFORCECCM = 0), Load changes between 0 mA and 10 mA 23
Max load current ILOAD_MAX 200 mA Low noise (LN) mode, Heavy Drive, T ≤ 85 °C 24
Max load current ILOAD_MAX 100 mA Low noise (LN) mode, Heavy Drive, T > 85 °C 24
Max load current ILOAD_MAX 75 µA Low power (LP) mode, LPCMPBIASEMxx = 0 24
Max load current ILOAD_MAX 10 mA Low power (LP) mode, LPCMPBIASEMxx = 3 24
DCDC nominal output capacitor CDCDC 1 4.7 4.7 µF 25% tolerance 24
DCDC nominal output inductor LDCDC 4.7 4.7 4.7 µH 20% tolerance 24
Resistance in Bypass mode RBYP 1.2 2.5 Ω 24
Backup supply voltage range VBU_VIN 1.8 3.8 V 25
AUXHFRCO frequency accuracy fAUXHFRCO_ACC -3 3 % At production calibrated frequencies, across supply voltage and temperature 40
ULFRCO oscillation frequency fULFRCO 0.88 1 1.12 kHz 40
Flash erase cycles before failure ECFLASH 10000 cycles 41
Word (32-bit) programming time tW_PROG 20 26 32 µs Burst write, 128 words, average time per word 41
Word (32-bit) programming time tW_PROG 59 68 83 µs Single word 41
Page erase time tPERASE 20 27 35 ms 41
Mass erase time tMERASE 20 27 35 ms 41
Supply voltage during flash erase and write VFLASH 1.62 3.6 V 41
Input leakage current IIOLEAK 0.1 40 nA All GPIO except LFXO pins, GPIO ≤ IOVDD, T ≤ 85 °C 42
Input leakage current IIOLEAK 0.1 60 nA LFXO Pins, GPIO ≤ IOVDD, T ≤ 85 °C 42
Input leakage current IIOLEAK 150 nA All GPIO except LFXO pins, GPIO ≤ IOVDD, T > 85 °C 42
Input leakage current IIOLEAK 300 nA LFXO Pins, GPIO ≤ IOVDD, T > 85 °C 42
Input leakage current on 5VTOL pads above IOVDD I5VTOLLEAK 3.3 15 µA IOVDD < GPIO ≤ IOVDD + 2 V 42
I/O pin pull-up/pull-down resistor RPUD 30 40 65 kΩ 42
Pulse width of pulses removed by the glitch suppression filter tIOGLITCH 15 25 45 ns 42

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. 126

CAD (KiCad official)

  • Symbol: EFM32TG11B520F128GQ80-B
  • Footprint: Package_QFP:TQFP-80_12x12mm_P0.5mm
  • 3D model: TQFP-80(12x12) (KiCad packages3D, STEP)
  • 3D model files: efm32tg11b520f128gq80-b-etched.step / efm32tg11b520f128gq80-b-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); efm32tg11b520f128gq80-b.step / efm32tg11b520f128gq80-b.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SILICON LABS datasheet (153 pp, sha256 24bd24b451bb61c6, retrieved 2026-10-26, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF