EDA Skillpack

@@ -9,7 +9,7 @@     "In2.Cu": 0.0152,     "B.Cu": 0.035   },-  "manufacturer": "Adom InstaPCB",+  "manufacturer": "3rd party fab",   "signalWidthMm": 0.25,   "clearanceMm": 0.2,   "viaDiameterMm": 0.8,

@@ -83,7 +83,7 @@ Heat consists only of the balanced cold conduction losses above. MOSFET losses e - **Shunt R32:** 58.5 A produces 1.71 W at nominal 0.5 mΩ. The BOM's 3 W description alone does not establish mounted derating or pulse survival. Obtain the exact manufacturer's derating and overload curves; verify Kelvin measurements under load. - **DC-link C2/C3:** The BOM lists two 330 µF/35 V capacitors, 30 mΩ ESR and 2.7 A ripple each at 100 kHz. Those are unverified BOM ratings for this review. Actual RMS ripple, frequency and temperature must be checked against exact manufacturer data. Do not equate motor current with capacitor ripple or assume perfect sharing. - **Auxiliary regulators:** TPSM365R6 and AP2112 output-current descriptions do not guarantee operation at that current on this layout. Determine actual 5 V/3.3 V loads and losses. [TI module](https://www.ti.com/product/TPSM365R6), [Diodes LDO](https://www.diodes.com/datasheet/download/AP2112.pdf)-- **Interfaces and fabrication:** Verify contact ampacity, solder assembly, minimum copper/plating, the U2 land pattern and InstaPCB clearance capability. The inherited DRC errors remain a release blocker independently of this power-path finding.+- **Interfaces and fabrication:** Verify contact ampacity, solder assembly, minimum copper/plating, the U2 land pattern and the 3rd party fab's clearance capability. The inherited DRC errors remain a release blocker independently of this power-path finding.  ## Concrete corrective pass 

@@ -75,7 +75,7 @@ Heat consists only of the balanced cold conduction losses above. MOSFET losses e - **Shunt R32:** 58.5 A produces 1.71 W at nominal 0.5 mΩ. The BOM's 3 W description alone does not establish mounted derating or pulse survival. Obtain the exact manufacturer's derating and overload curves; verify Kelvin measurements under load. - **DC-link C2/C3:** The BOM lists two 330 µF/35 V capacitors, 30 mΩ ESR and 2.7 A ripple each at 100 kHz. Those are unverified BOM ratings for this review. Actual RMS ripple, frequency and temperature must be checked against exact manufacturer data. Do not equate motor current with capacitor ripple or assume perfect sharing. - **Auxiliary regulators:** TPSM365R6 and AP2112 output-current descriptions do not guarantee operation at that current on this layout. Determine actual 5 V/3.3 V loads and losses. [TI module](https://www.ti.com/product/TPSM365R6), [Diodes LDO](https://www.diodes.com/datasheet/download/AP2112.pdf)-- **Interfaces and fabrication:** Verify contact ampacity, solder assembly, minimum copper/plating, the U2 land pattern and InstaPCB clearance capability. The inherited DRC errors remain a release blocker independently of this power-path finding.+- **Interfaces and fabrication:** Verify contact ampacity, solder assembly, minimum copper/plating, the U2 land pattern and the 3rd party fab's clearance capability. The inherited DRC errors remain a release blocker independently of this power-path finding.  ## Concrete corrective pass 

@@ -1632,7 +1632,7 @@ Used as a test point connection for pogo pins or other debugging tools. <class number="1" name="pwr" width="0.09" drill="0"> </class> </classes>-<designrules name="Adom-InstaPCB-4-Layer.edru" version="V1">+<designrules name="3rd-party-fab-4-Layer.edru" version="V1"> <rules> <rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes" />  <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes" />@@ -1695,7 +1695,7 @@ Used as a test point connection for pogo pins or other debugging tools. <param name="msDrill" value="0.15mm" /> <param name="dpMaxLengthDifference" value="10mm" /> <param name="dpGapFactor" value="2.5" />-<description language="en">Adom InstaPCB 4-Layer design rules+<description language="en">3rd party fab 4-Layer design rules  Board thickness: 1.6mm Copper weight: 1oz (35um)@@ -1714,8 +1714,8 @@ Min. track width and spacing (1 oz) 0.10 / 0.10 mm (4 / 4 mil)  Vias:-- Min 0.15mm via allowed on 4-layer now with InstaPCB-- We made preferred 0.25mm, although InstaPCB says 0.2 is preferred+- Min 0.15mm via allowed on 4-layer now at the 3rd party fab+- We made preferred 0.25mm, although the fab says 0.2 is preferred Min. Via hole size/diameter 4-layer: 0.15mm hole size / 0.25mm via diameter  Drill:@@ -1724,8 +1724,8 @@ Min. Non-plated holes - 0.50mm Holes with diameter ≥ 6.3 mm are CNC routed from a smaller drilled hole.  Annular Ring:-Vias: 0.1mm annular ring is InstaPCB min-Pads (through-hole parts): 0.18mm annular ring is InstaPCB min+Vias: 0.1mm annular ring is the fab's min+Pads (through-hole parts): 0.18mm annular ring is the fab's min However, they prefer 0.25mm annular ring or above  </description>

@@ -4,7 +4,7 @@   "type": "skill",   "title": "EDA Skillpack",   "brief": "All skills for all EDA capabilities across the Adom ecosystem.",-  "version": "0.2.3",+  "version": "0.2.4",   "hero": {     "type": "image",     "path": "docs/hero.png"

@@ -68,9 +68,9 @@ For a thermal plot with a cool distant lobe or a narrow copper neck, read `eda-t  Before routing or changing fabrication rules, check whether the user has already chosen a manufacturer and process in this conversation or the project requirements. Honor that choice without asking again. Otherwise, discover available profiles from `adom/pcb-design-rules` (or the selected bridge's rule-profile listing) and ask: -“Who would you like to manufacture this board? I can automatically load and verify the matching design rules—for example, InstaPCB, JLCPCB or PCBWay. You can also name another manufacturer or keep the current rules for now.”+“Who would you like to manufacture this board? I can automatically load and verify the matching design rules—for example, the 3rd party fab, JLCPCB or PCBWay. You can also name another manufacturer or keep the current rules for now.” -Offer only manufacturers with available profiles as automatic-loading choices. Explain briefly that the choice affects trace widths, clearances, drills/vias and other fabrication limits. Do not silently default to InstaPCB or choose the smallest limits. If the user is undecided, retain and label the current rules as provisional; continue inspection while waiting, and defer manufacturer-dependent route generation or rule replacement until a choice is made.+Offer only manufacturers with available profiles as automatic-loading choices. Explain briefly that the choice affects trace widths, clearances, drills/vias and other fabrication limits. Do not silently default to the 3rd party fab profile or choose the smallest limits. If the user is undecided, retain and label the current rules as provisional; continue inspection while waiting, and defer manufacturer-dependent route generation or rule replacement until a choice is made.  Once selected, resolve the profile for the actual layer count, process and copper assumptions. Ask a focused follow-up only if a missing process choice materially changes the rules. Load it through the selected CAD bridge, export/read back the active rules, and report the profile and meaningful limits before routing. Preserve stricter electrical and user constraints. If no compatible profile exists, explain what is missing and obtain a supplied or authoritative profile rather than inventing one. Switching manufacturers later requires revalidation of the existing board and may require rerouting.