EDA Skillpack

@@ -11,6 +11,7 @@ Read the entry for the user's task, then the owning package's current skill. The | Create and inspect footprints, pads and paste geometry | [adom-footprint](https://wiki.adom.inc/adom/adom-footprint) | | Component libraries and EDA format translation | [adom-lbr](https://wiki.adom.inc/adom/adom-lbr) | | Find and source board components | [adom-parts-search](https://wiki.adom.inc/adom/adom-parts-search) |+| Manufacturer and process-specific DRC profiles | [PCB Design Rules](https://wiki.adom.inc/adom/pcb-design-rules) | | Shared electrical routing and copper-pour decisions | [eda-electrical-routing](../skills/eda-electrical-routing/SKILL.md) | | Shared heat-spreading and bottleneck review | [eda-thermal-bottlenecks](../skills/eda-thermal-bottlenecks/SKILL.md) | | Copper retention for subtractive fabrication | [eda-copper-ablation](../skills/eda-copper-ablation/SKILL.md) |

@@ -62,3 +62,12 @@ For numerical comparisons, record source/load boundary conditions, copper thickn Record a net-by-net highlighted tour of the chosen regions and explain both the selected finish and its tradeoffs. A worked Fusion expansion, corrected area measurements and reproducible first-order model are in [the expansion report](https://wiki.adom.inc/adom/codex/files/docs/FUSION-THERMAL-EXPANSION.md).  For a thermal plot with a cool distant lobe or a narrow copper neck, read `eda-thermal-bottlenecks` and reroute suitable obstructing traces before accepting the thermal allocation.+++## Select and verify the fabrication profile++Before calculating routes, find the selected manufacturer's current process/layer-count profile in [adom/pcb-design-rules](https://wiki.adom.inc/adom/pcb-design-rules). Verify stackup and copper/process assumptions against the actual board. Use the selected bridge's rule-import workflow, export the active rules, and compare their values, scopes and enabled states with the selected profile. Native tools may add default rules; distinguish those from a failed import.++Apply stricter user or electrical requirements as a documented overlay, preserving larger existing limits. For example, a user-selected 0.1 mm isolation floor must not silently become 0.09 mm because a four-layer profile permits it. Do not treat fabrication spacing as voltage clearance or trace-width minima as a load rating.++Run a native baseline DRC before stripping or routing the working copy. Classify inherited footprint issues, route errors and potentially mis-scoped rules with concrete geometry. A same-net rule applied to all objects may flag intentional junctions; investigate its intended scope rather than silently disabling it. Diagnostic-profile results from an earlier demonstration are not evidence that the selected manufacturing profile passes. Report when footprint or profile decisions prevent a compliant routing result.