EDA Skillpack

@@ -1,3 +1,9 @@ # EDA Engineering -Shared PCB electrical, thermal and assembly reasoning for any AI and CAD bridge+Shared engineering skills for any AI using Fusion, KiCad or Altium. Install with `adom-wiki pkg install adom/eda-engineering`, then read `eda-engineering` and the relevant focused skill.++The package covers current/load reasoning, routing geometry, thermal pads and vias, copper-ablation retention, thermal-bottleneck rerouting, and assembly planning. It contains AI-neutral Markdown and no CAD application dependency. These are engineering workflows, not automatic board certification or prequalified machine recipes.++The [Astra/Fusion video progression](https://wiki.adom.inc/adom/codex/files/docs/ASTRA-FUSION.md) supplied worked examples. Device assumptions and measured outcomes stay with each example; reusable decisions live here.++The existing [EDA hub](https://wiki.adom.inc/adom/eda) remains the tool directory. Bridges own application verbs, native validation and saving/cleanup. AI skillpacks point here for shared reasoning. This avoids duplicated guidance and a bridge-to-hub dependency cycle.

@@ -0,0 +1,18 @@+---+name: eda-engineering+description: Shared engineering guidance for PCB routing, current-carrying paths, thermal copper, copper ablation and assembly planning across Fusion, KiCad and Altium. Use when designing or reviewing electrical and manufacturing behavior, independently of the AI provider.+---+# Shared EDA engineering++Use the selected CAD bridge for execution and native validation; this package owns the engineering reasoning. It does not install CAD applications or select an AI provider. User load/process requirements take precedence over worked-example defaults.++Read only the relevant skill:++- `eda-electrical-routing`: schematic/net checks, current budgets, widths, clean routing, thermal inventory, copper allocation and acceptance.+- `eda-thermal-bottlenecks`: use calculated heat flow to relocate obstructing traces, widen necks and preserve reference planes.+- `eda-copper-ablation`: retain permissible copper while preserving electrical isolation and reporting actual filled area.+- `eda-assembly-planning`: connect pad/mask/thermal decisions to placement, solder jetting or paste deposition, reflow and inspection requirements.++These skills are AI-neutral Markdown. Adom's package loader exposes them to supported AI runtimes; another runtime can read this file and `skills/*/SKILL.md` directly. Installing files does not update instructions already loaded in an existing conversation.++Fusion/KiCad/Altium-specific verbs and document lifecycle belong with their bridges. Shared principles should be maintained here and referenced by bridge/AI skillpacks, rather than copied into competing versions. The broader tool directory remains [adom/eda](https://wiki.adom.inc/adom/eda).

@@ -0,0 +1,5 @@+#!/bin/sh+set -eu+# The wiki package loader installs root and nested SKILL.md files for supported agents.+# No CAD installation, AI selection, personal configuration, or machine recipe is changed.+printf '%s\n' 'EDA engineering skills installed; read eda-engineering in your AI skill catalog.'

@@ -14,19 +14,56 @@     "name": "John Lauer",     "email": "[email protected]"   },-  "tags": [],+  "tags": [+    "eda",+    "pcb",+    "thermal",+    "routing",+    "assembly",+    "skills"+  ],   "license": "proprietary",   "visibility": {     "public": true   },-  "sample_prompts": [],-  "discovery_triggers": [],-  "discovery_pitch": null,+  "sample_prompts": [+    {+      "label": "Improve heat spreading",+      "prompt": "Find thermal bottlenecks on my PCB and reroute suitable crossing traces to improve heat spreading."+    }+  ],+  "discovery_triggers": [+    "improve pcb heat spreading",+    "reroute thermal bottlenecks",+    "pcb current capacity",+    "copper ablation",+    "plan pcb assembly"+  ],+  "discovery_pitch": "Use when routing or reviewing PCB electrical, thermal and assembly constraints with any CAD bridge.",   "metadata": {},   "created_at": "2026-09-07T12:56:14.529Z",   "updated_at": "2026-09-07T12:56:14.529Z",   "source_path": "SKILL.md",   "sub_skills": [],   "parent_app": null,-  "org": "adom"-}\ No newline at end of file+  "org": "adom",+  "description": "AI-neutral PCB electrical, thermal, copper-ablation and assembly planning skills.",+  "files": [+    "SKILL.md",+    "skills/**",+    "README.md",+    "install.sh",+    "uninstall.sh"+  ],+  "dependencies": {},+  "confirmed_user_skills": [+    "eda-electrical-routing",+    "eda-thermal-bottlenecks",+    "eda-copper-ablation",+    "eda-assembly-planning"+  ],+  "scripts": {+    "install": "./install.sh",+    "uninstall": "./uninstall.sh"+  }+}

@@ -0,0 +1,19 @@+---+name: eda-assembly-planning+description: Review PCB placement, solder-mask, thermal-pad and via decisions against pick-and-place, solder jetting or paste deposition, reflow and inspection requirements before preparing assembly outputs.+---+Parent skill: eda-engineering++# Connect layout decisions to the actual assembly process++This is a planning and review workflow, not a qualified machine recipe. Establish the assembler, equipment, material and component constraints before generating machine commands or claiming manufacturability.++For placement outputs, preserve reference designators, BOM variants, DNP status, package orientation, polarity, board origin, units and top/bottom conventions. Verify rotations against a known asymmetric part and the machine importer; mirrored bottom placement is not merely a sign change. Include fiducials, board support, component access and nozzle/tool clearances as required by the equipment.++For solder jetting or paste deposition, obtain the exact material and dispenser process window. Use the manufacturer's required deposit volume, wetting/keepouts, minimum features and substrate conditions. Do not infer jet shot count from exposed copper area or reuse a stencil recipe as a jetting program. Different solder jetting, paste jetting and adhesive dispensing processes are distinct.++For exposed pads and thermal vias, jointly assess heat conduction and solder wicking. Apply component and fabricator guidance for via tenting, plugging, filling/capping, paste segmentation, standoff and allowable voiding. A thermal-via pattern that improves a heat model may produce an unacceptable solder joint. Mask opening, copper opening and paste aperture are different geometries.++For reflow, use the solder material's process guidance and component temperature limits. Large heatsink pours increase local thermal mass; verify the profile at critical joints with measurements on a representative assembly. Do not manufacture an oven profile from a PCB heat-spreading plot. Plan inspection and rework access, including hidden-pad joints where the chosen acceptance process requires it.++Carry forward the layout revision/hash, BOM and assembly variant, placement convention, mask/paste outputs, fabrication notes and unresolved constraints. Use native CAD exports and the relevant equipment bridge; do not invent bridge verbs. Broader automation should be added only with equipment-specific evidence and validation.

@@ -0,0 +1,33 @@+---+name: eda-copper-ablation+description: Route PCBs for copper ablation by retaining copper on every layer, including intentionally floating islands when requested. Measure native filled copper coverage, preserve electrical isolation, and record reproducible CAD demonstrations.+---+Parent skill: eda-engineering++# PCB routing for copper ablation++For subtractive ablation, routing connectivity is only one objective. Starting from copper-clad material, maximize retained copper subject to electrical, geometric and manufacturing constraints. A trace-only layout with empty surrounding FR4 does not satisfy a request for minimum copper removal.++Establish the process's minimum isolation-channel width and manufacturing tolerance. Treat this as a fabrication limit, not a voltage-independent clearance rule. Preserve larger applicable clearances. Establish maximum differential working voltage, switching/transient peaks, environment, coating, altitude and insulation category before claiming electrical safety. Clearance through air and creepage along a surface are separate checks; consult current primary guidance and the applicable end-product standard. Never invent a universal voltage-to-gap threshold from nominal air breakdown strength.++Keep an isolated copy of the source and the trace-only routed checkpoint. Recheck the selected host, bridge pin, active document and actual editor identity before mutation. Use the current app bridge's supported native polygon/pour interface. Never infer failure from a timeout without checking state.++## Copper strategy++- Use net-connected copper where it has an appropriate electrical function. Retain islands only when the user's ablation objective permits floating copper; do not apply this policy to unrelated board work.+- A polygon's nominal net name does not prove every filled contour is connected. Distinguish connected copper from physically floating orphan regions after refill.+- Floating copper is conductive material with an uncontrolled potential. Do not insert it into required isolation barriers or count it as insulating distance. Preserve appropriate keepouts around sensitive nodes and any required high-voltage separation.+- Fill each active copper layer within the board boundary, accounting for edge clearance, drills, keepouts, net clearances and local width limits. Do not change stackup or reduce an existing electrical clearance merely to increase coverage.+- In Fusion, solid polygons with `orphans=yes` retain otherwise discarded isolated regions. Thermal connections, solid connections, polygon rank and minimum neck width affect the fill and must be selected deliberately. Use native refill and inspect actual results.+- Maximal ground fill is one candidate, not proof of globally optimal copper use. Broader power copper and local net-assigned regions can improve electrical behavior; narrow pre-existing power routes are not qualified merely by filling ground around them.++## Verification and measurement++Force a native refill before export, connectivity checks or area measurement. Outlines and stale cached fill are not sufficient. Preserve the native exported filled geometry, DRC report, board hash, input rules and chosen process constraints.++Compute copper area from the union of filled polygons, tracks, pads and vias, clipped to the board outline; subtract polygon holes and actual drill voids. Avoid double-counting overlaps. Report each copper layer and the total projected area across layers. State the denominator and geometric approximations. Report the area-to-remove reduction relative to the same trace-only board, not just the increase in copper percentage. Area is not a measured machining-time reduction: scan strategy, channel passes, spot size and motion overhead also matter.++Compare fresh native DRC and connectivity with the baseline under the same rule profile. Preserve pre-existing error signatures and separately report new errors. Check copper islands, shorts, clearances and narrow residual gaps. Check voltage-specific requirements separately; native DRC proves only the rules actually encoded.++If an inherited rule is inconsistent with intended connectivity, diagnose it on comparison copies, disclose the exact change, and retain the unmodified reference. Never hide violations by suppressing rules to improve the video result.+

@@ -0,0 +1,64 @@+---+name: eda-electrical-routing+description: Route or review a PCB with electrical constraints, power and ground pours, clean signal geometry, and copper-retention goals for subtractive or copper-ablation fabrication. Use before claiming an AI-routed board is electrically ready or recording a production-oriented routing demo.+---+Parent skill: eda-engineering++# Electrical constraints before route generation++Start from the schematic, actual pad/net assignments, BOM and manufacturer requirements. A wiki overview can be wrong. Compare schematic and PCB membership; identify omitted parts, duplicate pads, alternative footprints and assembly variants. Preserve the original and previous demonstration as separate checkpoints.++Establish the fabrication and load contract: layer stackup, copper thickness, minimum reliable isolation gap, edge clearance, plated holes/vias, permitted neck widths, supply tolerance, channel currents, simultaneous loads, duty cycle, 5 V load and temperature limits. Infer only from explicit design evidence; label provisional values. Do not silently substitute generic signal defaults for power nets. Request missing specifications while continuing independent review.++Component ratings set permissible limits; they do not establish the actual external load. Derive explicit resistive loads from voltage and resistance where valid, but obtain solenoid/motor and external connector loads from the load specification. Sum simultaneous branch loads at shared trunks and returns, including converter input power and losses. A fabrication minimum gap is not automatically the selected electrical clearance. Treat heavier copper and plated vias as design options that still require actual thickness/plating assumptions.++Classify nets before optimizing geometry:++- Supply and load returns: allocate current-carrying corridors/pours and adequate interlayer connections. Inspect the narrowest cross-section and all pad/thermal/via bottlenecks, not only total copper area.+- Switching nodes: keep the high-di/dt loop short and wide, and the high-dv/dt copper compact; large pours can increase capacitive coupling and emissions.+- Feedback and gate control: preserve the relevant return/reference and avoid noisy power paths. Check gate-drive voltage and switching demands against guaranteed device specifications.+- USB and other differential signals: route as a pair using the actual stackup, controlled spacing and a continuous return plane. Check stubs, branches, via transitions and endpoint constraints. Total net copper length is not the end-to-end pair skew.+- Ordinary signals: prefer short, consistent-width paths and few intentional bends. Smooth search-grid stair steps only when clearance and connectivity remain verified.++# Routing appearance and thermal planning++Default to horizontal and vertical runs joined by 45-degree transitions. Optimize the number of bends and vias as well as route length; do not leave arbitrary-angle links or search-grid stair steps just because they pass DRC. Preserve intentional pad escapes, component rotations, differential spacing and electrical constraints. Constrain planner escapes and post-processing too: an unrestricted line-of-sight shortcut can undo an eight-direction search. Remove redundant collinear vertices, and recheck each shortcut against fixed and newly generated copper. Audit segment angles numerically, then inspect the actual board visually. Report any exceptions rather than claiming every segment is orthogonal/45-degree. Smooth tangent arcs are an optional alternative when the native CAD API, clearances and fabrication process support them; use actual native arcs and verify their radius and tangency rather than approximating curves with many tiny segments.++Before allocating routes and pours, inventory heat-producing and high-current components, exposed pads, heatsink tabs, existing thermal-via arrays and thermal features embedded in footprints. Determine each thermal pad's electrical net from the schematic and manufacturer data; do not assume an exposed pad or heatsink tab is ground. Estimate relevant conduction, switching and regulator losses under the load contract and document uncertainty.++Reserve useful connected copper beneath and around those parts, and connect to an appropriate opposite-side or internal spreading region with deliberate thermal vias where supported. Preserve existing thermal vias and understand their net and assembly purpose before altering them. Check via drill/plating, pitch, solder wicking and whether filled/capped vias are required. A thermal pad's solid connection may matter more than total board copper area. Use available external copper for heat spreading while preserving routing corridors, return planes and manufacturer keepouts; do not enlarge a high-dv/dt switching node indiscriminately.++Where the existing stackup has inner layers, consider routing suitable signals there to preserve external heat-spreading copper, while maintaining their reference planes and power paths. Do not invent inner layers on a two-layer board or change the stackup without a design decision. External copper can improve heat transfer, but bottom-side cooling is not automatically best: enclosure, airflow, mounting, insulation and contact surfaces determine the benefit. Quantify improvements where supported; copper area alone is not a junction-temperature result.++# Copper retention for ablation++When the fabrication goal is to remove as little copper as possible, optimize the actual filled copper area on each layer inside the permitted board boundary. Broad power regions can lower resistance; connected ground can occupy unused space and support return paths. Do not give every net an unrestricted board-wide pour. Partition by electrical function, reserve isolation/return corridors, and use explicit zone priorities.++Check minimum isolation against the process, voltage and reliability requirements. Prevent floating islands and unusably thin copper slivers. Retain unconnected copper only when the manufacturing/electrical specification explicitly allows it. Respect antenna, chassis, isolation and component keepouts. Thermal-relief and via choices must support both current flow and assembly.++On disposable diagnostic copies, remove thin parallel power traces and refill to determine whether pours independently connect the load pads. A large zone outline can still fragment around other-net pads; shape separate supply and switched-return corridors. Do not accept the diagnostic copy until native connectivity, thermal and clearance checks pass.++Measure retained copper from refilled polygons, tracks and pads, with unions to avoid double-counting overlap. Report both layer coverage and estimated removed area; coverage alone does not prove lower laser time, which also depends on process passes, travel, contour length and setup. Do not infer a fabrication-ready current rating from trace width alone.++# Acceptance and narration++Use the native CAD application’s copper refill and DRC on each accepted candidate (KiCad or Fusion as applicable). Check schematic/PCB parity and ERC separately, classify inherited issues, and keep evidence for remaining manufacturing, thermal and signal-integrity decisions. Do not suppress real rules to obtain a clean report. Confirm the same result on the actual live replay.++For a demo, expose concrete decisions: the load budget, chosen power paths, compact switching loop, paired USB route, ground continuity, copper-retention measurements and final tests. Explain what was precomputed. Use the selected CAD bridge and recording workflow for the recorded/narrated artifact. A routing demonstration or simulation is not a substitute for required physical load, transient and USB testing.++Worked public example and evidence: [the BQ routing evidence](https://wiki.adom.inc/adom/codex/files/docs/ELECTRICAL-ROUTING.md). It records failed pour partitions, independent load-pour connectivity checks, thermal-spoke repair, schematic parity and unresolved interface/component limits. Recalculate its board-specific choices for each new design.+++# Expand thermal copper after routing++After initial routing, explicitly revisit connected heat-spreading regions and grow them into remaining permissible area. Allocate copper using component losses and thermal-pad net membership; reserve the ground paths and cooling area of other heat-producing parts. Preserve compact switching nodes, return planes, isolation corridors and fabrication constraints. Larger net areas can replace previously connected ground copper: report that loss and compare the affected ground thermal paths rather than presenting all reassigned copper as newly added cooling surface. Without actual losses and enclosure data, call the result a candidate allocation, not a globally optimal thermal design.++Measure the refilled connected union, subtract drill voids, exclude floating islands, and count regions shared by devices once. Use different variable names for global drill voids and per-polygon hole rings. Validate the measurement against simple known shapes and the native exported board; if a measurement bug is found, recalculate both sides and disclose the correction. Examine necks and thermal-via connections: large area behind a narrow link can contribute less than its projected area suggests.++Compare mask-covered and exposed copper using both convection and radiation. Removing a thin mask does not add meaningful surface area; its small film resistance may be outweighed by the low emissivity of bright copper. Use actual surface-finish/material data or labeled sensitivity assumptions, not a universal claim that exposing copper improves cooling. Partial openings require a spatial analysis or must be explicitly labeled an area-weighted approximation. A contact heatsink, thermal interface material or chassis path is a separate conduction problem, including electrical isolation and assembly consequences.++For numerical comparisons, record source/load boundary conditions, copper thickness, mask thickness and conductivity, convection, emissivity, ambient and radiative surroundings. Distinguish bottom-surface heat-path calculations from total board dissipation and junction temperature. Check energy balance, resolution sensitivity and a narrow-neck case; include package/via/FR4/other-layer/enclosure omissions. A fixed source-temperature result is not an allowable power rating or a measured temperature improvement.++Record a net-by-net highlighted tour of the chosen regions and explain both the selected finish and its tradeoffs. A worked Fusion expansion, corrected area measurements and reproducible first-order model are in [the expansion report](https://wiki.adom.inc/adom/codex/files/docs/FUSION-THERMAL-EXPANSION.md).++For a thermal plot with a cool distant lobe or a narrow copper neck, read `eda-thermal-bottlenecks` and reroute suitable obstructing traces before accepting the thermal allocation.

@@ -0,0 +1,22 @@+---+name: eda-thermal-bottlenecks+description: Review PCB thermal plots and narrow copper connections, then reroute suitable obstructing traces across layers to improve heat spreading while preserving electrical and assembly constraints.+---+Parent skill: eda-engineering++# Let thermal results drive the next routing pass++A geometrically connected copper island can be thermally ineffective. A cool remote lobe may indicate poor conduction from the device, not successful device cooling. Total filled area, zero airwires and DRC are insufficient thermal acceptance criteria.++1. Preserve the prior board and its native refilled copper, rule profile and thermal assumptions. Identify the exact device thermal pad and electrical net. Inventory neighboring heat sources and actual losses where known.+2. Find cuts caused by other-net traces, clearances, antipads, relief spokes and slivers. Inspect the narrowest effective heat path, not just the polygon outline. For a uniform neck, `Rth ~= length/(conductivity * thickness * width)` is a screening approximation, not package-to-ambient resistance. Resolve narrow geometry in the mesh and test resolution sensitivity.+3. Identify each obstructing trace's electrical role before moving it. Evaluate a local layer hop, a short same-layer detour, or relocating an entire branch. Prefer broad exterior heat paths when useful for the actual enclosure. Reuse valid existing plated endpoints/vias when possible; extra vias are not intrinsically better.+4. Preserve switching-loop inductance, feedback sensing, differential constraints, current capacity and return continuity. A signal moved inside a ground pour creates an internal slot; check that the cure does not cut another critical return or thermal path. Through-via antipads affect every spanned layer. Do not add layers or assume a high-current path fits a single small via.+5. Refill and run native DRC/connectivity on each candidate. Compare whole-path length, bend angles, minimum width, via count, reference-plane continuity, connected thermal area and affected neighboring nets. Retain failures as evidence; do not weaken rules to accept a candidate.+6. Compare both geometries with identical boundary conditions. At fixed source temperature, compare heat flow; at fixed power with a suitable full model, compare temperatures. Report tradeoffs, model omissions and actual operating data still missing. A bottom-sheet estimate is not a junction prediction or physical test.+7. Record the before/after choke point, highlight the displaced signal on its new layer, show the newly continuous thermal region, and explain measured validation. Label computed plots and precomputed routes clearly. Verify the actual replay matches the analyzed candidate.+8. Checkpoint the accepted native document and close this task's completed scratch copies. Exporting a source artifact may not clear the application's modified/recovery state.++Do not default to removing solder mask. Assess the actual finish, radiation, convection, insulation and any contact heatsink separately. Retained floating copper is not connected heat-spreading area.++Primary guidance: [TI motor-driver board layout](https://www.ti.com/lit/an/slva959b/slva959b.pdf), including continuous copper planes and thermal-via connections. Apply device-specific datasheets and the actual stackup. The [Fusion expansion example](https://wiki.adom.inc/adom/codex/files/docs/FUSION-THERMAL-EXPANSION.md) illustrates why increasing area without rerouting can leave constrictions.

@@ -0,0 +1,4 @@+#!/bin/sh+set -eu+# Package-owned skill removal is handled by the wiki package loader.+printf '%s\n' 'EDA engineering package uninstall requested.'