EDA Skillpack

@@ -15,3 +15,9 @@ Fusion, KiCad and Altium may keep their own skillpacks inside their bridges. Bro The showcase pairs Fusion, Altium and KiCad with Adom’s browser tools: [adom-symbol](https://wiki.adom.inc/adom/adom-symbol) for schematic symbols, [adom-footprint](https://wiki.adom.inc/adom/adom-footprint) for pads and paste geometry, [adom-lbr](https://wiki.adom.inc/adom/adom-lbr) for symbol/footprint/3D libraries and format conversion, and [adom-parts-search](https://wiki.adom.inc/adom/adom-parts-search) for component sourcing. These are real application captures; the collage illustrates the broader workflow, not a claim that every tool has completed the Fusion routing demonstration.  ![Desktop EDA and Adom web tools](docs/showcase-collage.png)++## Route visibly with shared engineering guidance++Ask your AI: “Use `eda-visible-routing` from the [EDA Skillpack](https://wiki.adom.inc/adom/eda-engineering) to route my working board copy visibly, with clean bends, electrical priorities, expanded copper pours and thermal bottleneck review. Use my selected EDA bridge for execution and native validation.”++Read the [skill](skills/eda-visible-routing/SKILL.md) directly or install the skillpack with `adom-wiki pkg install adom/eda-engineering`. It supports any AI and delegates tool-specific operations to the appropriate bridge.

@@ -10,8 +10,9 @@ This package is both an index of independently owned skills and a home for share  Start with the [skill directory](references/skill-directory.md) to find the relevant owner. Read only the entrypoints and follow-ups needed for the user's task. Respect the selected tool and existing project; use its bridge for live execution, native validation and document lifecycle. -The initial bundled shared skills are:+The bundled shared skills are: +- [Visible routing and copper optimization](skills/eda-visible-routing/SKILL.md): live routing, clean bends, electrical priorities, copper expansion and thermal review. - [Electrical routing](skills/eda-electrical-routing/SKILL.md): current budgets, route geometry and copper-pour decisions. - [Thermal bottlenecks](skills/eda-thermal-bottlenecks/SKILL.md): review connected heat-spreading paths and suitable reroutes. - [Copper ablation](skills/eda-copper-ablation/SKILL.md): retain permissible copper while preserving isolation.

@@ -4,7 +4,7 @@   "type": "skill",   "title": "EDA Skillpack",   "brief": "All skills for all EDA capabilities across the Adom ecosystem.",-  "version": "0.1.0",+  "version": "0.1.1",   "hero": {     "type": "billboard",     "headline": "EDA Skillpack",@@ -61,7 +61,8 @@     "eda-electrical-routing",     "eda-thermal-bottlenecks",     "eda-copper-ablation",-    "eda-assembly-planning"+    "eda-assembly-planning",+    "eda-visible-routing"   ],   "scripts": {     "install": "./install.sh",

@@ -12,6 +12,7 @@ Read the entry for the user's task, then the owning package's current skill. The | Component libraries and EDA format translation | [adom-lbr](https://wiki.adom.inc/adom/adom-lbr) | | Find and source board components | [adom-parts-search](https://wiki.adom.inc/adom/adom-parts-search) | | Manufacturer and process-specific DRC profiles | [PCB Design Rules](https://wiki.adom.inc/adom/pcb-design-rules) |+| Live routing and copper optimization | [eda-visible-routing](../skills/eda-visible-routing/SKILL.md) | | Shared electrical routing and copper-pour decisions | [eda-electrical-routing](../skills/eda-electrical-routing/SKILL.md) | | Shared heat-spreading and bottleneck review | [eda-thermal-bottlenecks](../skills/eda-thermal-bottlenecks/SKILL.md) | | Copper retention for subtractive fabrication | [eda-copper-ablation](../skills/eda-copper-ablation/SKILL.md) |

@@ -0,0 +1,19 @@+---+name: eda-visible-routing+description: Route a PCB visibly with clean trace geometry, electrical priorities, expanded net-connected copper pours and thermal bottleneck review. Use for live AI routing in Fusion, KiCad, Altium or another supported EDA tool.+---+# Visible PCB routing and copper optimization++Use this shared workflow with the selected EDA tool's bridge skills for native commands, document lifecycle and validation. It is AI-neutral and applies to real boards, not only demonstrations. Do not switch providers, replay a saved plan, or record a video unless the user requested it. State whether geometry is freshly calculated or replayed.++Before edits, inspect the actual board and stackup, preserve the original, and save a working copy when rerouting an existing design. Read [eda-electrical-routing](../eda-electrical-routing/SKILL.md) for current budgets, sensitive signals and manufacturer selection. Honor an existing manufacturer choice; otherwise ask, then load and read back the matching process/layer-count rules. Keep stricter electrical and user constraints. A fabrication minimum is not a voltage-clearance or current-capacity rating.++Route visibly, one net at a time, using predominantly horizontal and vertical segments with 45-degree bends. Curved transitions are an option when supported and appropriate. Electrical constraints take priority over appearance. Prioritize power paths, return paths, current capacity and sensitive signals; allocate their corridors before filling remaining space. Use the bridge's supported progress UI to explain the current net, significant calculations and checks without obscuring the board. Verify actual geometry as it appears; a command acceptance alone is not proof of a completed route.++Inspect exposed pads, thermal vias and heat-producing components before allocating copper. Verify each thermal pad's net from the actual design and component documentation. Build and expand appropriate net-connected pours where space permits. Preserve isolation, antenna/keepout areas, return continuity and sensitive-node constraints; larger copper is not always appropriate, especially on switching nodes.++Read [eda-thermal-bottlenecks](../eda-thermal-bottlenecks/SKILL.md) when optimizing heat spreading. Inspect narrow connections between copper regions: a large remote region may contribute little through a thin neck. Consider moving suitable obstructing traces to another layer using vias to improve the connected copper path. Check the resulting return path, via capacity, clearance and layer availability; preserve footprint thermal vias. Compare connected area and neck dimensions before and after native refill, rather than counting all same-net polygon area as equally useful heatsinking. Distinguish geometry improvements from validated temperature predictions.++For copper-ablation fabrication, read [eda-copper-ablation](../eda-copper-ablation/SKILL.md). Minimize unnecessary copper removal within the applicable electrical and manufacturing constraints. Prefer useful connected copper. Retain floating copper only when requested or permitted by the selected process and electrical requirements; report it separately from useful net-connected copper.++Save meaningful checkpoints. Refill copper, run native DRC and connectivity checks, and read back the result. Report measured connectivity, violations and significant tradeoffs; distinguish inherited issues from new ones. Disclose bridge or stackup limitations rather than substituting an unsupported layer model or claiming completion.