EDA Skillpack

@@ -0,0 +1,21 @@+---+name: eda-board-3d-comparison+description: >-+  Compare original and redesigned PCB assemblies in the native EDA 3D viewer. Use for show my board in 3D, compare component placement, inspect stacked modules, explain symmetry or check assembly access.+user-invocable: true+---+# Native 3D placement comparison++Create or update native 3D derivatives from the verified original and candidate 2D boards. Confirm document identities and current source linkage; preserve accepted 2D geometry. Verify that the viewer contains the actual board and populated package models. Identify missing/placeholder models. An external visualization is not evidence that the requested native viewer worked.++Inspect application state after slow generation or timeout before retrying. A new 3D document can exist even when the transport reply timed out. Save newly generated task documents promptly. In Fusion, consult its bridge's 3D/electronics and cloud-save skills; discover `fusion_show_3d_board`, `fusion_view` and document schemas rather than assuming command support.++Record both complete assemblies from the same board orientation, camera path and scale. Automatic fit can produce different scales because invisible geometry or assembly extents differ. Use identical explicit orthographic camera settings for comparative top views, and verify the recorded frames. Include oblique views to show heights and stacked modules.++When daughterboards obscure the main PCB, temporarily hide the corresponding assembly occurrences in BOTH copies. State that visibility is changed for inspection, not that parts are removed. Preserve the original visibility map, including already-hidden objects, and restore it afterward. Do not blindly turn every occurrence on. Recheck and save the restored assembly state.++Explain actual coordinate/rotation differences in functional groups. Pair full-board context with closeups or editorial callouts. Label overlays so they are not confused with native selection, simulation or measured clearance. Acknowledge symmetry, grouping, assembly access, increased vias and other disadvantages, rather than claiming every new placement is superior.++Look for daughterboard/base-component collisions, connector/wiring access, mating orientation, contact alignment, standoffs, pin lengths, edge clearance and service access. Visual inspection can reveal concerns, but use native interference checks, tolerances and approved mechanical envelopes before declaring fit. Missing models and unspecified pin/press-fit tolerances remain open items. Thermal conclusions need electrical losses and cooling assumptions; 3D appearance alone is not a thermal result.++Preserve both native derivatives, source snapshots, camera settings, model inventory and comparison evidence. Close only completed task scratch documents after saving; leave other work alone.

@@ -0,0 +1,21 @@+---+name: eda-component-placement+description: >-+  Calculate PCB component placement from nets, footprints, power paths and mechanical interfaces. Use for move all components off the board, place my PCB, optimize placement, preserve connector grids, or compare layout symmetry.+user-invocable: true+---+# Calculate and verify component placement++Work on a saved copy. Inventory the real outline, layers, element and net identities, pad geometry, rotations, footprint bodies, courtyard/keepout data and 3D envelopes. Ask which positions may move. Never infer that electrical connectivity permits moving mounting holes, edge connectors or daughterboard mating patterns.++For Adom Molecules, consult the current Molecule and contact standards and source module documentation. Preserve the required corner contacts and grid, orientation/polarity and relative mating pattern of stackable modules. Distinguish a nest/interface footprint from the actual daughterboard envelope: a valid 2D mating grid does not prove installed clearance or assembly access.++Inspect the functional groups first: power entry/protection, switches, charger/regulator, inductor, decoupling, sensitive feedback/sense, digital interfaces and external contacts. Use component datasheets and board-specific load constraints. Identify exposed pads, existing thermal-via fields and high-loss/high-current parts before consuming their copper space. Keep fast current loops and their returns compact; keep switching nodes away from sensitive sensing. Do not claim quantified improvement without an appropriate model.++Define hard constraints separately from objectives. Hard constraints include board boundary, keepouts, required interfaces, pad/body clearances, orientation and assembly access. Objectives can include connection length, feasible escape paths, via count, power-loop geometry, copper continuity, symmetry, alignment and legible grouping. State the priorities. Symmetry is a useful human-facing objective; sacrificing it should be an explicit tradeoff, not an unexamined artifact.++Place constrained interfaces and critical component clusters, then remaining parts. Reserve escape corridors before dense packing. Evaluate body and pad geometry after rotation; refine broad bounding-box checks with actual outlines where necessary. Search multiple placements or improve a candidate iteratively. A selected heuristic candidate is not a global optimum.++Use joint escape assignment for congested fine-pitch pins: independent nearest-via choices can consume each other's exits. Couple placement feedback to routing failures and thermal bottlenecks. Keep trial candidates separate; only commit an accepted placement to the visible final replay.++Read back the native element positions and rotations, net membership and outline. Audit interface/grid requirements. Compare original and new coordinates for the explanation. If footprint drills or contact definitions were updated, record those as separate changes. Finish with native 3D assembly review and native DRC after routing, not just a placement screenshot.

@@ -0,0 +1,23 @@+---+name: eda-design-summary-video+description: >-+  Make a narrated evidence-based video of PCB placement, routing, validation and native 3D comparison. Use for show the team what the AI did, summarize my PCB redesign, record a before and after, or make an engineering meeting video.+user-invocable: true+---+# Show the engineering work in a concise video++Use the selected bridge's native recording capabilities and the shared demo/recording and speech skills. Record actual CAD windows. Preserve raw takes and edits; do not create an animation of traces and present it as live editor execution. For public sharing, verify source/design visibility and keep unrelated private windows or boards out of the capture.++Plan the story around visible evidence: original board; proved stripped/off-board state if requested; new placement; native trace/via commits; pours and revisions; measured native checks; full native 3D assembly and comparison. Explain the criteria and decisions a user can assess. Distinguish precomputed candidate replay from fresh calculation occurring live. A concise rationale and calculation result is sufficient; do not expose private internal chain-of-thought.++Log start/stop IDs and native operations. Stop recording in a finally block and collect the actual finalized file. Encoded duration can differ from wall-clock logs, so locate cut points from frames. Inspect transitions, last route additions and final repair; never use a fully routed shot as proof of an unrouted placement state. Keep unsuccessful takes as evidence.++Remove idle intervals and label the actual action speed. Repeated inspection camera clips should say replay; still frames should say hold. For comparisons use matching scale/orientation, readable labels and a responsive presentation. Show important component moves with native selection or clearly editorial callouts. Preserve enough context that viewers can identify the tool and board.++Write narration from verified results. State what changed, why, what failed and was corrected, what the checks measured, and what remains unqualified. Use Adom's shared TTS skill for narration assets, normalize speech loudness, check clipping and transitions, and leave a short final reading hold after the last words. Do not cut speech to meet an arbitrary duration.++Validate the final media with ffprobe, a full decode, sampled sequential frames and an audio-ending check. Save a manifest of sources, intervals, playback factors, captions, narration and file hash. Retain the original output when revising an ending.++Transfer the finished MP4 to the user's actual host and verify its bytes. Open through the host's video association when requested; verify exact filename and playback state in the player. A container link or successful launch response alone does not prove playback.++For a meeting page, lead with a responsive native HTML video element: `<video width="100%" controls playsinline preload="metadata" src="ABSOLUTE_PUBLISHED_MEDIA_URL"></video>`. Add a short outcome summary, chapter timestamps, measured results/limits, original source and shared skill links. Verify published playback metadata and page layout. Publishing source skills is distinct from publishing an installable skillpack; do not promise package installation unless the released tarball actually contains them.

@@ -0,0 +1,20 @@+---+name: eda-placement-routing-review+description: >-+  Coordinate an independent PCB placement, trace routing, native 3D review and narrated comparison. Use for place and route my board, start from an empty board, compare AI and human placement, or show the whole PCB design process.+user-invocable: true+---+# Placement, routing and review++Use this AI-neutral workflow with the user's selected EDA bridge. Read `eda-component-placement`, `eda-visible-routing`, `eda-board-3d-comparison` and, when a video is requested, `eda-design-summary-video`. Consult the EDA skill directory for tool-owned commands and Molecule/manufacturing guidance. These are methods, not a bundled optimizer or a promise of automatic signoff.++1. Discover the live desktop, CAD version, bridge capabilities, active document and concurrent ownership. Preserve intentional development pins. Save an immutable reference and create a uniquely named task copy before edits.+2. Ask which manufacturer/process the user wants. Load its actual rule profile, read it back, and keep stricter user/electrical constraints. Ask about voltage/transients, current, stackup/copper and cooling when needed for power or thermal claims. Missing inputs do not prevent a labelled placement study; they prevent qualification claims.+3. Establish outline, mounting/mating patterns, connector access, stackable modules, keepouts and mechanical constraints. Use current domain-owned standards, not a remembered demo dimension.+4. Record the original. When the task requests fresh placement, strip routes/vias/pours from the copy, move eligible components off-board, then inspect native counts/positions. Preserve nets, pads, devices and approved outline. Show proof of the initial state.+5. Calculate placement and routing candidates from the actual netlist/footprints. Distinguish fresh calculation from replay of a saved solution. Save rejected candidates and reasons. Check footprint bodies, pads, rotations and routing feasibility before showing an accepted candidate as final.+6. Apply accepted placement and routes visibly in bounded groups. Preserve checkpoints and call/revision logs. Show short progress explanations with the application's existing status surface. Do not present private internal reasoning; show design criteria, measurable checks and accepted decisions.+7. Refill and run native DRC on the actual replay. Verify placement, netlist, copper per net/layer, via identity and final native connectivity. Same-net copper overlap is not always a native junction. Consult native-connectivity-conformance and fine-pitch-fanout skills.+8. Compare native 3D assemblies and explain actual moves, including disadvantages. Save documents, restore temporary visibility changes and make a concise narrated summary when requested.++Acceptance evidence includes the original/candidate source, applied rule profile, interface/placement audit, native DRC, actual geometry read-back, 3D model/visibility state, and video provenance. Report baseline and introduced issues separately. A clean DRC is not ERC, synchronized schematic/PCB, current capacity, thermal performance, mechanical fit or CAM qualification. Say which remain open.