component
dsPIC33FJ16GS402-I
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Microchip Tech Microcontroller Units (MCUs/MPUs/SOCs), SOIC-28-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
dsPIC33FJ16GS402-I
Microchip Tech · Microcontroller Units (MCUs/MPUs/SOCs) · SOIC-28-300mil
dsPIC33FJ16GS402-I from Microchip Tech, in a SOIC-28-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | MCLR | input | Active-low Master Clear (Reset) input to the device, also used for programming and debugging; 5V tolerant. |
| 2 | AN0/RA0 | bidirectional | Analog input channel 0 shared with PORTA bidirectional I/O RA0. |
| 3 | AN1/RA1 | bidirectional | Analog input channel 1 shared with PORTA bidirectional I/O RA1. |
| 4 | AN2/RA2 | bidirectional | Analog input channel 2 shared with PORTA bidirectional I/O RA2. |
| 5 | AN3/RP0/CN0/RB0 | bidirectional | Analog input 3, remappable pin RP0, change notification CN0 and PORTB I/O RB0. |
| 6 | AN4/RP9/CN9/RB9 | bidirectional | Analog input 4, remappable pin RP9, change notification CN9 and PORTB I/O RB9. |
| 7 | AN5/RP10/CN10/RB10 | bidirectional | Analog input 5, remappable pin RP10, change notification CN10 and PORTB I/O RB10. |
| 8 | VSS | power_in | Ground reference for logic and I/O pins; must always be connected. |
| 9 | OSC1/CLKIN/AN6/RP1/CN1/RB1 | bidirectional | Oscillator crystal input or external clock input (CLKIN), shared with analog input AN6, RP1, CN1 and RB1. |
| 10 | OSC2/CLKO/AN7/RP2/CN2/RB2 | bidirectional | Oscillator crystal output or CLKO, shared with analog input AN7, RP2, CN2 and RB2. |
| 11 | PGED2/INT0/RP3/CN3/RB3 | bidirectional | ICSP data I/O for programming/debugging channel 2, shared with external interrupt 0, RP3, CN3 and RB3. |
| 12 | PGEC2/RP4/CN4/RB4 | bidirectional | ICSP clock input for programming/debugging channel 2, shared with RP4, CN4 and RB4; 5V tolerant. |
| 13 | VDD | power_in | Positive supply for peripheral logic and I/O pins, 3.0V to 3.6V. |
| 14 | PGED3/RP8/CN8/RB8 | bidirectional | ICSP data I/O for programming/debugging channel 3, shared with RP8, CN8 and RB8; 5V tolerant. |
| 15 | PGEC3/RP15/CN15/RB15 | bidirectional | ICSP clock input for programming/debugging channel 3, shared with RP15, CN15 and RB15; 5V tolerant. |
| 16 | TDO/RP5/CN5/RB5 | bidirectional | JTAG test data output shared with RP5, CN5 and RB5. |
| 17 | PGED1/TDI/SCL1/RP6/CN6/RB6 | bidirectional | ICSP data I/O channel 1, JTAG TDI and I2C1 clock, shared with RP6, CN6 and RB6; 5V tolerant. |
| 18 | PGEC1/SDA1/RP7/CN7/RB7 | bidirectional | ICSP clock input channel 1 and I2C1 data, shared with RP7, CN7 and RB7; 5V tolerant. |
| 19 | VSS | power_in | Ground reference for logic and I/O pins; must always be connected. |
| 20 | VCAP | passive | CPU logic filter capacitor connection; needs a low-ESR (<5 Ohm) 4.7 uF to 10 uF capacitor to ground and must not be connected to VDD. |
| 21 | TMS/PWM3H/RP11/CN11/RB11 | bidirectional | JTAG test mode select and PWM3 high output, shared with RP11, CN11 and RB11; 5V tolerant. |
| 22 | TCK/PWM3L/RP12/CN12/RB12 | bidirectional | JTAG test clock input and PWM3 low output, shared with RP12, CN12 and RB12; 5V tolerant. |
| 23 | PWM2H/RP13/CN13/RB13 | bidirectional | PWM2 high output shared with RP13, CN13 and RB13; 5V tolerant. |
| 24 | PWM2L/RP14/CN14/RB14 | bidirectional | PWM2 low output shared with RP14, CN14 and RB14; 5V tolerant. |
| 25 | PWM1H/RA4 | bidirectional | PWM1 high output shared with PORTA I/O RA4; 5V tolerant. |
| 26 | PWM1L/RA3 | bidirectional | PWM1 low output shared with PORTA I/O RA3; 5V tolerant. |
| 27 | AVSS | power_in | Ground reference for analog modules, connected to VSS; must always be connected. |
| 28 | AVDD | power_in | Positive supply for analog modules, connected to VDD; must be connected at all times. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-28-300mil |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 28 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VDD | 3 | 3.6 | V | Industrial and Extended | 289 | |
| RAM Data Retention Voltage | VDR | 1.8 | V | 289 | |||
| VDD Rise Rate to Ensure Internal Power-on Reset Signal | SVDD | 0.03 | V/ms | 0V-3.0V in 0.1 seconds | 289 | ||
| Operating temperature (Industrial) | TA | -40 | 85 | °C | Industrial | 289 | |
| POR Threshold | VPOR | 1.8 | V | nominal | 93 | ||
| BOR Threshold | VBOR | 2.5 | V | nominal | 93 | ||
| POR Extension Time | TPOR | 30 | µs | maximum | 93 | ||
| BOR Extension Time | TBOR | 100 | µs | maximum | 93 |
CAD (KiCad official)
- Symbol:
dsPIC33FJ16GS402-I - Footprint:
Package_SO:SOIC-28W_7.5x17.9mm_P1.27mm - 3D model: SOIC-28-300mil (KiCad packages3D, STEP)
- 3D model files:
dspic33fj16gs402-i-etched.step/dspic33fj16gs402-i-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dspic33fj16gs402-i.step/dspic33fj16gs402-i.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (398 pp, sha256
3caa457741930be8, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).