# dsPIC33EP16GS502-I

**Microchip Tech** · MICROCHIP · QFN-28-EP(6x6)

dsPIC33EP16GS502-I from Microchip Tech, in a QFN-28-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol and footprint from KiCad-official CAD; the 3D model is generated from the datasheet's package dimensions.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RA2 | bidirectional | PORTA I/O shared with analog input AN2, PGA1P3, PGA2P2 and comparator inputs CMP1C/CMP2A; analog by default after Reset. |
| 2 | RB0 | bidirectional | PORTB I/O shared with AN3, PGA2P3, CMP1D/CMP2B and remappable pin RP32. |
| 3 | RB9 | bidirectional | PORTB I/O shared with AN4, CMP2C/CMP3A, constant-current output ISRC4 and remappable pin RP41. |
| 4 | RB10 | bidirectional | PORTB I/O shared with AN5, CMP2D/CMP3B, constant-current output ISRC3 and remappable pin RP42. |
| 5 | VSS | power_in | Ground reference for logic and I/O pins; must always be connected. |
| 6 | RB1 | bidirectional | PORTB I/O shared with OSC1/CLKI oscillator input, AN6, CMP3C/CMP4A, ISRC2 and remappable pin RP33. |
| 7 | RB2 | bidirectional | PORTB I/O shared with OSC2/CLKO oscillator output, AN7, PGA1N2, CMP3D/CMP4B and remappable pin RP34. |
| 8 | RB3 | bidirectional | PORTB I/O shared with PGED2 programming data, AN18, DACOUT1, INT0 and remappable pin RP35. |
| 9 | RB4 | bidirectional | 5V-tolerant PORTB I/O shared with PGEC2 programming clock, ADTRG31 ADC trigger input, EXTREF1 and remappable pin RP36. |
| 10 | VDD | power_in | Positive supply for peripheral logic and I/O pins (3.0V to 3.6V operating range); must always be connected. |
| 11 | RB8 | bidirectional | 5V-tolerant PORTB I/O shared with PGED3 programming data, SDA2, PWM fault input FLT31 and remappable pin RP40. |
| 12 | RB15 | bidirectional | 5V-tolerant PORTB I/O shared with PGEC3 programming clock, SCL2 and remappable pin RP47. |
| 13 | RB5 | bidirectional | PORTB I/O shared with JTAG TDO, AN19, PGA2N2 and remappable pin RP37. |
| 14 | RB6 | bidirectional | PORTB I/O shared with PGED1 programming data, JTAG TDI, AN20, SCL1 and remappable pin RP38. |
| 15 | RB7 | bidirectional | PORTB I/O shared with PGEC1 programming clock, AN21, SDA1 and remappable pin RP39. |
| 16 | VSS | power_in | Ground reference for logic and I/O pins; must always be connected. |
| 17 | VCAP | passive | CPU logic filter capacitor connection; needs a low-ESR (<0.5 ohm) capacitor greater than 4.7 uF (10 uF recommended) to ground and must not be connected to VDD. |
| 18 | RB11 | bidirectional | 5V-tolerant PORTB I/O shared with JTAG TMS, PWM3H output and remappable pin RP43. |
| 19 | RB12 | bidirectional | 5V-tolerant PORTB I/O shared with JTAG TCK, PWM3L output and remappable pin RP44. |
| 20 | RB13 | bidirectional | 5V-tolerant PORTB I/O shared with PWM2H output and remappable pin RP45. |
| 21 | RB14 | bidirectional | 5V-tolerant PORTB I/O shared with PWM2L output and remappable pin RP46. |
| 22 | RA4 | bidirectional | 5V-tolerant PORTA I/O shared with PWM1H output. |
| 23 | RA3 | bidirectional | 5V-tolerant PORTA I/O shared with PWM1L output. |
| 24 | AVSS | power_in | Ground reference for analog modules; must be connected at all times. |
| 25 | AVDD | power_in | Positive supply for analog modules; must be connected at all times. |
| 26 | MCLR | input | 5V-tolerant active-low Master Clear (Reset) input, also used for device programming and debugging. |
| 27 | RA0 | bidirectional | PORTA I/O shared with analog input AN0, PGA1P1 and comparator input CMP1A. |
| 28 | RA1 | bidirectional | PORTA I/O shared with analog input AN1, PGA1P2, PGA2P1 and comparator input CMP1B. |
| 29 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-28-EP(6x6) |
| Category | Embedded Processors & Controllers |
| Pins | 29 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Ambient temperature under bias |  | -40 |  | 125 | °C |  | 303 |
| Storage temperature |  | -65 |  | 150 | °C |  | 303 |
| Voltage on VDD with respect to VSS | VDD | -0.3 |  | 4 | V |  | 303 |
| Voltage on any 5V tolerant pin with respect to VSS when VDD >= 3.0V |  | -0.3 |  | 5.5 | V | VDD >= 3.0V | 303 |
| Voltage on any 5V tolerant pin with respect to VSS when VDD < 3.0V |  | -0.3 |  | 3.6 | V | VDD < 3.0V | 303 |
| Supply Voltage | VDD | 3 |  | 3.6 | V |  | 304 |
| Maximum MIPS |  |  |  | 70 | MIPS | VDD 3.0V to 3.6V; -40°C to +85°C | 304 |
| Operating Ambient Temperature Range (Industrial Temperature Devices) | TA | -40 |  | 85 | °C | Industrial Temperature Devices | 304 |
| Operating Junction Temperature Range (Industrial Temperature Devices) | TJ | -40 |  | 125 | °C | Industrial Temperature Devices | 304 |
| Package Thermal Resistance, 28-Pin QFN-S 6x6x0.9 mm | JA |  | 30 |  | °C/W | Note 1: junction to ambient, achieved by package simulations | 304 |
| RAM Retention Voltage | VDR | 1.8 |  |  | V | -40ºC | 305 |
| RAM Retention Voltage | VDR | 2 |  |  | V | +25ºC, +85ºC, +125ºC | 305 |
| VDD Rise Rate to Ensure Internal Power-on Reset Signal | SVDD | 1 |  |  | V/ms | 0V-3V in 3 ms | 305 |
| External Filter Capacitor Value (CEFC) | CEFC | 4.7 | 10 |  | F | Capacitor must have a low series resistance (<1 ohm) | 305 |
| OSC2 Pin capacitive loading | COSCO |  |  | 15 | pF | In XT and HS modes, when external clock is used to drive OSC1 | 315 |
| All I/O Pins and OSC2 capacitive loading | CIO |  |  | 50 | pF | EC mode | 315 |
| SCLx, SDAx capacitive loading | CB |  |  | 400 | pF | In I2C mode | 315 |

## CAD (land: KiCad; 3D: generated from the datasheet)

- Symbol: `dsPIC33EP16GS502-I`
- Footprint: `Package_DFN_QFN:QFN-28-1EP_6x6mm_P0.65mm_EP4.8x4.8mm`
- 3D model: QFN-28-EP(6x6), generated on the KiCad land (body 6 x 6 mm, terminals on the pads, 0.5 mm tall, datasheet A, nominal). KiCad's stock model for this land is taller than the datasheet allows, so the model is generated from the datasheet drawing; the dimensions come from the datasheet drawing where it was read and are defaults otherwise (see provenance.model_3d_generated), not the manufacturer's CAD (STEP)
- 3D model files: `dspic33ep16gs502-i-mm-etched.step` / `dspic33ep16gs502-i-mm-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dspic33ep16gs502-i-mm.step` / `dspic33ep16gs502-i-mm.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Tech datasheet](https://ww1.microchip.com/downloads/en/DeviceDoc/70005127d.pdf) (390 pp, sha256 `69126c50f4a4115e`, retrieved 2026-11-13, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** land: KiCad official libraries (CC-BY-SA 4.0); 3D: generated from the datasheet's package dimensions (provenance.model_3d_generated).

[Datasheet PDF](docs/dspic33ep16gs502-i-mm-datasheet.pdf)