DSP56F803BU80E

{
  "slug": "dsp56f803bu80e",
  "version": "0.1.0",
  "type": "component",
  "description": "NXP Semicon NXP MCU, LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "embedded processors & controllers",
    "dsp56f803bu80e",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
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    "README.md",
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    "dsp56f803bu80e.kicad_mod",
    "dsp56f803bu80e.glb",
    "dsp56f803bu80e.step",
    "dsp56f803bu80e.lbr",
    "docs/hero.png",
    "docs/dsp56f803bu80e-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "dsp56f803bu80e-hero.glb",
    "dsp56f803bu80e-hero.overlay.json",
    "dsp56f803bu80e-etched.glb"
  ],
  "component": {
    "mpn": "DSP56F803BU80E",
    "manufacturer": "NXP Semicon",
    "package": "LQFP-100(14x14)",
    "pin_count": 100,
    "category": "Embedded Processors & Controllers",
    "subcategory": "NXP MCU",
    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/a536f91a3671920cc79838cc47449adc.pdf",
    "parts": {
      "symbol": "dsp56f803bu80e.kicad_sym",
      "footprint": "dsp56f803bu80e.kicad_mod",
      "model_3d": "dsp56f803bu80e-hero.glb",
      "model_3d_plain": "dsp56f803bu80e-etched.glb",
      "model_3d_step": "dsp56f803bu80e-etched.step",
      "model_3d_step_plain": "dsp56f803bu80e.step",
      "lbr": "dsp56f803bu80e.lbr"
    },
    "distributor_links": {
      "lcsc": "C1337891",
      "digikey": "DSP56F803BU80E-ND",
      "mouser": "841-DSP56F803BU80E"
    },
    "distributor_check": {
      "checked_at": "2026-10-30T17:08:29Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "DSP56F803BU80E-ND",
        "status": "found",
        "lifecycle": "Obsolete"
      },
      "mouser": {
        "pn": "841-DSP56F803BU80E",
        "status": "found",
        "lifecycle": "Obsolete"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "D10",
        "type": "bidirectional",
        "description": "External data bus bit D10, tri-stated when the external bus is inactive and internal pull-ups may be active."
      },
      {
        "number": "2",
        "name": "D11",
        "type": "bidirectional",
        "description": "External data bus bit D11, tri-stated when the external bus is inactive and internal pull-ups may be active."
      },
      {
        "number": "3",
        "name": "D12",
        "type": "bidirectional",
        "description": "External data bus bit D12, tri-stated when the external bus is inactive and internal pull-ups may be active."
      },
      {
        "number": "4",
        "name": "D13",
        "type": "bidirectional",
        "description": "External data bus bit D13, tri-stated when the external bus is inactive and internal pull-ups may be active."
      },
      {
        "number": "5",
        "name": "D14",
        "type": "bidirectional",
        "description": "External data bus bit D14, tri-stated when the external bus is inactive and internal pull-ups may be active."
      },
      {
        "number": "6",
        "name": "D15",
        "type": "bidirectional",
        "description": "External data bus bit D15, tri-stated when the external bus is inactive and internal pull-ups may be active."
      },
      {
        "number": "7",
        "name": "A0",
        "type": "output",
        "description": "Address bus bit A0 specifies the address for external program or data memory accesses and is tri-stated during reset."
      },
      {
        "number": "8",
        "name": "VDD",
        "type": "power_in",
        "description": "Provides power to the internal structures of the chip; all VDD pins should be attached to VDD."
      },
      {
        "number": "9",
        "name": "VSS",
        "type": "power_in",
        "description": "GND for the internal structures of the chip; all VSS pins should be attached to VSS."
      },
      {
        "number": "10",
        "name": "A1",
        "type": "output",
        "description": "Address bus bit A1 specifies the address for external program or data memory accesses and is tri-stated during reset."
      },
      {
        "number": "11",
        "name": "A2",
        "type": "output",
        "description": "Address bus bit A2 specifies the address for external program or data memory accesses and is tri-stated during reset."
      },
      {
        "number": "12",
        "name": "A3",
        "type": "output",
        "description": "Address bus bit A3 specifies the address for external program or data memory accesses and is tri-stated during reset."
      },
      {
        "number": "13",
        "name": "A4",
        "type": "output",
        "description": "Address bus bit A4 specifies the address for external program or data memory accesses and is tri-stated during reset."
      },
      {
        "number": "14",
        "name": "A5",
        "type": "output",
        "description": "Address bus bit A5 specifies the address for external program or data memory accesses and is tri-stated during reset."
      },
      {
        "number": "15",
        "name": "A6",
        "type": "bidirectional",
        "description": "Address bus bit A6 for external memory accesses; alternately Port E GPIO, with the address bus as the default function after reset."
      },
      {
        "number": "16",
        "name": "A7",
        "type": "bidirectional",
        "description": "Address bus bit A7 for external memory accesses; alternately Port E GPIO, with the address bus as the default function after reset."
      },
      {
        "number": "17",
        "name": "A8",
        "type": "bidirectional",
        "description": "Address bus bit A8 for external memory accesses; alternately Port A GPIO, with the address bus as the default function after reset."
      },
      {
        "number": "18",
        "name": "A9",
        "type": "bidirectional",
        "description": "Address bus bit A9 for external memory accesses; alternately Port A GPIO, with the address bus as the default function after reset."
      },
      {
        "number": "19",
        "name": "A10",
        "type": "bidirectional",
        "description": "Address bus bit A10 for external memory accesses; alternately Port A GPIO, with the address bus as the default function after reset."
      },
      {
        "number": "20",
        "name": "A11",
        "type": "bidirectional",
        "description": "Address bus bit A11 for external memory accesses; alternately Port A GPIO, with the address bus as the default function after reset."
      },
      {
        "number": "21",
        "name": "A12",
        "type": "bidirectional",
        "description": "Address bus bit A12 for external memory accesses; alternately Port A GPIO, with the address bus as the default function after reset."
      },
      {
        "number": "22",
        "name": "A13",
        "type": "bidirectional",
        "description": "Address bus bit A13 for external memory accesses; alternately Port A GPIO, with the address bus as the default function after reset."
      },
      {
        "number": "23",
        "name": "VDD",
        "type": "power_in",
        "description": "Provides power to the internal structures of the chip; all VDD pins should be attached to VDD."
      },
      {
        "number": "24",
        "name": "PS",
        "type": "output",
        "description": "Program Memory Select, asserted low for external program memory access."
      },
      {
        "number": "25",
        "name": "DS",
        "type": "output",
        "description": "Data Memory Select, asserted low for external data memory access."
      },
      {
        "number": "26",
        "name": "A14",
        "type": "bidirectional",
        "description": "Address bus bit A14 for external memory accesses; alternately Port A GPIO, with the address bus as the default function after reset."
      },
      {
        "number": "27",
        "name": "A15",
        "type": "bidirectional",
        "description": "Address bus bit A15 for external memory accesses; alternately Port A GPIO, with the address bus as the default function after reset."
      },
      {
        "number": "28",
        "name": "VSS",
        "type": "power_in",
        "description": "GND for the internal structures of the chip; all VSS pins should be attached to VSS."
      },
      {
        "number": "29",
        "name": "WR",
        "type": "output",
        "description": "Write Enable, asserted low during external memory write cycles and can connect directly to the WE pin of a Static RAM."
      },
      {
        "number": "30",
        "name": "RD",
        "type": "output",
        "description": "Read Enable, asserted low during external memory read cycles and can connect directly to the OE pin of a Static RAM or ROM."
      },
      {
        "number": "31",
        "name": "IRQA",
        "type": "input",
        "description": "External interrupt request A, a Schmitt-trigger input that can be programmed as level-sensitive or negative-edge-triggered."
      },
      {
        "number": "32",
        "name": "IRQB",
        "type": "input",
        "description": "External interrupt request B, a Schmitt-trigger input that can be programmed as level-sensitive or negative-edge-triggered."
      },
      {
        "number": "33",
        "name": "TCS",
        "type": "input",
        "description": "Schmitt pin reserved for factory use that must be tied to VSS for normal use."
      },
      {
        "number": "34",
        "name": "TCK",
        "type": "input",
        "description": "JTAG/OnCE test clock input, listed as a Schmitt-trigger input; its timing is shown in Figure 3-29."
      },
      {
        "number": "35",
        "name": "TMS",
        "type": "input",
        "description": "JTAG/OnCE test mode select input, listed as a Schmitt-trigger input."
      },
      {
        "number": "36",
        "name": "TDI",
        "type": "input",
        "description": "JTAG/OnCE test data input, listed as a Schmitt-trigger input."
      },
      {
        "number": "37",
        "name": "TDO",
        "type": "output",
        "description": "JTAG/OnCE test data output; its valid-data timing is shown in Figure 3-29."
      },
      {
        "number": "38",
        "name": "TRST",
        "type": "input",
        "description": "JTAG/OnCE test reset input, listed as a Schmitt-trigger input; its timing is shown in Figure 3-30."
      },
      {
        "number": "39",
        "name": "VCAPC",
        "type": "passive",
        "description": "Connect to a 2.2 µF or greater bypass capacitor to bypass the core logic voltage regulator, which is required for proper chip operation."
      },
      {
        "number": "40",
        "name": "ISA0",
        "type": "input",
        "description": "PWM input ISA0, listed as a Schmitt-trigger input."
      },
      {
        "number": "41",
        "name": "ISA1",
        "type": "input",
        "description": "PWM input ISA1, listed as a Schmitt-trigger input."
      },
      {
        "number": "42",
        "name": "ISA2",
        "type": "input",
        "description": "PWM input ISA2, listed as a Schmitt-trigger input."
      },
      {
        "number": "43",
        "name": "FAULTA0",
        "type": "input",
        "description": "PWM fault input used by the fault protection and cycle-by-cycle current limiting of the PWM module."
      },
      {
        "number": "44",
        "name": "MSCAN_TX",
        "type": "output",
        "description": "CAN transmit output of the CAN interface, which is CAN Version 2.0 A/B-compliant."
      },
      {
        "number": "45",
        "name": "FAULTA1",
        "type": "input",
        "description": "PWM fault input used by the fault protection and cycle-by-cycle current limiting of the PWM module."
      },
      {
        "number": "46",
        "name": "MSCAN_RX",
        "type": "input",
        "description": "CAN receive input of the CAN interface, listed as a Schmitt-trigger input."
      },
      {
        "number": "47",
        "name": "FAULTA2",
        "type": "input",
        "description": "PWM fault input used by the fault protection and cycle-by-cycle current limiting of the PWM module."
      },
      {
        "number": "48",
        "name": "VREF",
        "type": "power_in",
        "description": "ADC reference pin in the ADC port; its limits are given in Table 2-15, which is not in the provided pages."
      },
      {
        "number": "49",
        "name": "AN0",
        "type": "input",
        "description": "ADC analog input; with the ADC not sampling, input current is limited to ±15 µA with VIN between VSSA and VDDA."
      },
      {
        "number": "50",
        "name": "AN1",
        "type": "input",
        "description": "ADC analog input; with the ADC not sampling, input current is limited to ±15 µA with VIN between VSSA and VDDA."
      },
      {
        "number": "51",
        "name": "AN2",
        "type": "input",
        "description": "ADC analog input; with the ADC not sampling, input current is limited to ±15 µA with VIN between VSSA and VDDA."
      },
      {
        "number": "52",
        "name": "AN3",
        "type": "input",
        "description": "ADC analog input; with the ADC not sampling, input current is limited to ±15 µA with VIN between VSSA and VDDA."
      },
      {
        "number": "53",
        "name": "AN4",
        "type": "input",
        "description": "ADC analog input; with the ADC not sampling, input current is limited to ±15 µA with VIN between VSSA and VDDA."
      },
      {
        "number": "54",
        "name": "AN5",
        "type": "input",
        "description": "ADC analog input; with the ADC not sampling, input current is limited to ±15 µA with VIN between VSSA and VDDA."
      },
      {
        "number": "55",
        "name": "AN6",
        "type": "input",
        "description": "ADC analog input; with the ADC not sampling, input current is limited to ±15 µA with VIN between VSSA and VDDA."
      },
      {
        "number": "56",
        "name": "AN7",
        "type": "input",
        "description": "ADC analog input; with the ADC not sampling, input current is limited to ±15 µA with VIN between VSSA and VDDA."
      },
      {
        "number": "57",
        "name": "XTAL",
        "type": "bidirectional",
        "description": "Crystal oscillator output that should be connected to an 8MHz crystal or ceramic resonator; it can also be driven by an external clock source."
      },
      {
        "number": "58",
        "name": "EXTAL",
        "type": "input",
        "description": "External crystal oscillator input that should be connected to an 8MHz crystal or ceramic resonator."
      },
      {
        "number": "59",
        "name": "VSSA",
        "type": "power_in",
        "description": "Analog ground pin for the analog portion of the chip."
      },
      {
        "number": "60",
        "name": "VDDA",
        "type": "power_in",
        "description": "Dedicated analog power pin that should be connected to a low noise 3.3V supply."
      },
      {
        "number": "61",
        "name": "VDD",
        "type": "power_in",
        "description": "Provides power to the internal structures of the chip; all VDD pins should be attached to VDD."
      },
      {
        "number": "62",
        "name": "VDD",
        "type": "power_in",
        "description": "Provides power to the internal structures of the chip; all VDD pins should be attached to VDD."
      },
      {
        "number": "63",
        "name": "VSS",
        "type": "power_in",
        "description": "GND for the internal structures of the chip; all VSS pins should be attached to VSS."
      },
      {
        "number": "64",
        "name": "PHASEA0 (TA0)",
        "type": "input",
        "description": "Quadrature decoder phase A input, alternately Quad Timer A pin TA0; the decoder captures all four transitions on the two-phase inputs."
      },
      {
        "number": "65",
        "name": "PHASEB0 (TA1)",
        "type": "input",
        "description": "Quadrature decoder phase B input, alternately Quad Timer A pin TA1; the decoder captures all four transitions on the two-phase inputs."
      },
      {
        "number": "66",
        "name": "VDD",
        "type": "power_in",
        "description": "Provides power to the internal structures of the chip; all VDD pins should be attached to VDD."
      },
      {
        "number": "67",
        "name": "VSS",
        "type": "power_in",
        "description": "GND for the internal structures of the chip; all VSS pins should be attached to VSS."
      },
      {
        "number": "68",
        "name": "INDEX0 (TA2)",
        "type": "input",
        "description": "Quadrature decoder index input, alternately Quad Timer A pin TA2."
      },
      {
        "number": "69",
        "name": "HOME0 (TA3)",
        "type": "input",
        "description": "Quadrature decoder home input, alternately Quad Timer A pin TA3."
      },
      {
        "number": "70",
        "name": "PWMA0",
        "type": "output",
        "description": "PWM output with sufficient drive to directly drive standard opto-isolators; the PWM supports complementary and independent outputs for six PWM outputs in total."
      },
      {
        "number": "71",
        "name": "PWMA1",
        "type": "output",
        "description": "PWM output with sufficient drive to directly drive standard opto-isolators; the PWM supports complementary and independent outputs for six PWM outputs in total."
      },
      {
        "number": "72",
        "name": "PWMA2",
        "type": "output",
        "description": "PWM output with sufficient drive to directly drive standard opto-isolators; the PWM supports complementary and independent outputs for six PWM outputs in total."
      },
      {
        "number": "73",
        "name": "PWMA3",
        "type": "output",
        "description": "PWM output with sufficient drive to directly drive standard opto-isolators; the PWM supports complementary and independent outputs for six PWM outputs in total."
      },
      {
        "number": "74",
        "name": "PWMA4",
        "type": "output",
        "description": "PWM output with sufficient drive to directly drive standard opto-isolators; the PWM supports complementary and independent outputs for six PWM outputs in total."
      },
      {
        "number": "75",
        "name": "PWMA5",
        "type": "output",
        "description": "PWM output with sufficient drive to directly drive standard opto-isolators; the PWM supports complementary and independent outputs for six PWM outputs in total."
      },
      {
        "number": "76",
        "name": "TXD0 (GPIOE0)",
        "type": "output",
        "description": "SCI0 transmit data output, alternately Port E GPIO."
      },
      {
        "number": "77",
        "name": "RXD0 (GPIOE1)",
        "type": "input",
        "description": "SCI0 receive data input, alternately Port E GPIO."
      },
      {
        "number": "78",
        "name": "EXTBOOT",
        "type": "input",
        "description": "Schmitt-trigger input listed in the Table 3-4 notes; its full function is in the Table 2-9 continuation, which is not in the provided pages."
      },
      {
        "number": "79",
        "name": "RESET",
        "type": "input",
        "description": "Schmitt-trigger input listed in the Table 3-4 notes; its full function is in the Table 2-9 continuation, which is not in the provided pages."
      },
      {
        "number": "80",
        "name": "DE",
        "type": "bidirectional",
        "description": "JTAG/OnCE port signal whose timing is shown in Figure 3-31 (debug event); full function is in Table 2-17, not in the provided pages."
      },
      {
        "number": "81",
        "name": "CLKO",
        "type": "output",
        "description": "Buffered clock output whose source is selected by CLKOSEL[4:0] in CLKOSR, or which can be disabled by that register."
      },
      {
        "number": "82",
        "name": "TD1",
        "type": "bidirectional",
        "description": "Quad Timer D pin, part of the Quad Timer module port; its limits are in Table 2-16, not in the provided pages."
      },
      {
        "number": "83",
        "name": "TD2",
        "type": "bidirectional",
        "description": "Quad Timer D pin, part of the Quad Timer module port; its limits are in Table 2-16, not in the provided pages."
      },
      {
        "number": "84",
        "name": "SS (GPIOE7)",
        "type": "bidirectional",
        "description": "SPI slave select, alternately Port E GPIO; the SPI port can be used as GPIO if SPI is not required."
      },
      {
        "number": "85",
        "name": "MISO (GPIOE6)",
        "type": "bidirectional",
        "description": "SPI master-in/slave-out data pin, alternately Port E GPIO; the SPI port can be used as GPIO if SPI is not required."
      },
      {
        "number": "86",
        "name": "MOSI (GPIOE5)",
        "type": "bidirectional",
        "description": "SPI master-out/slave-in data pin, alternately Port E GPIO; the SPI port can be used as GPIO if SPI is not required."
      },
      {
        "number": "87",
        "name": "SCLK (GPIOE4)",
        "type": "bidirectional",
        "description": "SPI serial clock pin, alternately Port E GPIO; the SPI port can be used as GPIO if SPI is not required."
      },
      {
        "number": "88",
        "name": "VCAPC",
        "type": "passive",
        "description": "Connect to a 2.2 µF or greater bypass capacitor to bypass the core logic voltage regulator, which is required for proper chip operation."
      },
      {
        "number": "89",
        "name": "D0",
        "type": "bidirectional",
        "description": "External data bus bit D0, tri-stated when the external bus is inactive and internal pull-ups may be active."
      },
      {
        "number": "90",
        "name": "D1",
        "type": "bidirectional",
        "description": "External data bus bit D1, tri-stated when the external bus is inactive and internal pull-ups may be active."
      },
      {
        "number": "91",
        "name": "D2",
        "type": "bidirectional",
        "description": "External data bus bit D2, tri-stated when the external bus is inactive and internal pull-ups may be active."
      },
      {
        "number": "92",
        "name": "VDD",
        "type": "power_in",
        "description": "Provides power to the internal structures of the chip; all VDD pins should be attached to VDD."
      },
      {
        "number": "93",
        "name": "VSS",
        "type": "power_in",
        "description": "GND for the internal structures of the chip; all VSS pins should be attached to VSS."
      },
      {
        "number": "94",
        "name": "D3",
        "type": "bidirectional",
        "description": "External data bus bit D3, tri-stated when the external bus is inactive and internal pull-ups may be active."
      },
      {
        "number": "95",
        "name": "D4",
        "type": "bidirectional",
        "description": "External data bus bit D4, tri-stated when the external bus is inactive and internal pull-ups may be active."
      },
      {
        "number": "96",
        "name": "D5",
        "type": "bidirectional",
        "description": "External data bus bit D5, tri-stated when the external bus is inactive and internal pull-ups may be active."
      },
      {
        "number": "97",
        "name": "D6",
        "type": "bidirectional",
        "description": "External data bus bit D6, tri-stated when the external bus is inactive and internal pull-ups may be active."
      },
      {
        "number": "98",
        "name": "D7",
        "type": "bidirectional",
        "description": "External data bus bit D7, tri-stated when the external bus is inactive and internal pull-ups may be active."
      },
      {
        "number": "99",
        "name": "D8",
        "type": "bidirectional",
        "description": "External data bus bit D8, tri-stated when the external bus is inactive and internal pull-ups may be active."
      },
      {
        "number": "100",
        "name": "D9",
        "type": "bidirectional",
        "description": "External data bus bit D9, tri-stated when the external bus is inactive and internal pull-ups may be active."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: MPN mismatch: the exact suffix DSP56F803BU80E is not in the provided text. Table 1 lists DSP56F803BU; Pages 18–24 are not in the provided text. These contain the detailed descriptions for Tables 2-10 to; Pin descriptions for TD1 and TD2 (Quad Timer D), TRST/TCK/TMS/TDI/TDO/DE (JTAG/OnCE), and VREF (ADC)",
          "86/100 pins cited to the wrong page (name found elsewhere): ['1:D10@p17', '2:D11@p17', '3:D12@p17', '4:D13@p17']"
        ],
        "pages_sent": 17,
        "cost_usd": 0.1387,
        "at": "2026-10-30T17:08:10"
      },
      "datasheet": {
        "url": "https://datasheet.lcsc.com/datasheet/pdf/a536f91a3671920cc79838cc47449adc.pdf",
        "pages": 57,
        "sha256": "ff676f1917189cb5",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 100,
        "described": 100,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "dsp56f803bu80e.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          16.0,
          16.0,
          1.5
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "51720097260ffba41c3062f85f67623721102fa535901c47cb555a1f444feeb3",
        "checked": "2026-10-30",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "dsp56f803bu80e-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          16.0,
          16.0,
          1.5
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "6b152d1ebb4b5c10bd7357493325b5c6271e613facf8eb387b6762458e22e3e7",
        "checked": "2026-10-30",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}