DSP56F803BU80E from NXP Semicon, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	D10	bidirectional	External data bus bit D10, tri-stated when the external bus is inactive and internal pull-ups may be active.
2	D11	bidirectional	External data bus bit D11, tri-stated when the external bus is inactive and internal pull-ups may be active.
3	D12	bidirectional	External data bus bit D12, tri-stated when the external bus is inactive and internal pull-ups may be active.
4	D13	bidirectional	External data bus bit D13, tri-stated when the external bus is inactive and internal pull-ups may be active.
5	D14	bidirectional	External data bus bit D14, tri-stated when the external bus is inactive and internal pull-ups may be active.
6	D15	bidirectional	External data bus bit D15, tri-stated when the external bus is inactive and internal pull-ups may be active.
7	A0	output	Address bus bit A0 specifies the address for external program or data memory accesses and is tri-stated during reset.
8	VDD	power_in	Provides power to the internal structures of the chip; all VDD pins should be attached to VDD.
9	VSS	power_in	GND for the internal structures of the chip; all VSS pins should be attached to VSS.
10	A1	output	Address bus bit A1 specifies the address for external program or data memory accesses and is tri-stated during reset.
11	A2	output	Address bus bit A2 specifies the address for external program or data memory accesses and is tri-stated during reset.
12	A3	output	Address bus bit A3 specifies the address for external program or data memory accesses and is tri-stated during reset.
13	A4	output	Address bus bit A4 specifies the address for external program or data memory accesses and is tri-stated during reset.
14	A5	output	Address bus bit A5 specifies the address for external program or data memory accesses and is tri-stated during reset.
15	A6	bidirectional	Address bus bit A6 for external memory accesses; alternately Port E GPIO, with the address bus as the default function after reset.
16	A7	bidirectional	Address bus bit A7 for external memory accesses; alternately Port E GPIO, with the address bus as the default function after reset.
17	A8	bidirectional	Address bus bit A8 for external memory accesses; alternately Port A GPIO, with the address bus as the default function after reset.
18	A9	bidirectional	Address bus bit A9 for external memory accesses; alternately Port A GPIO, with the address bus as the default function after reset.
19	A10	bidirectional	Address bus bit A10 for external memory accesses; alternately Port A GPIO, with the address bus as the default function after reset.
20	A11	bidirectional	Address bus bit A11 for external memory accesses; alternately Port A GPIO, with the address bus as the default function after reset.
21	A12	bidirectional	Address bus bit A12 for external memory accesses; alternately Port A GPIO, with the address bus as the default function after reset.
22	A13	bidirectional	Address bus bit A13 for external memory accesses; alternately Port A GPIO, with the address bus as the default function after reset.
23	VDD	power_in	Provides power to the internal structures of the chip; all VDD pins should be attached to VDD.
24	PS	output	Program Memory Select, asserted low for external program memory access.
25	DS	output	Data Memory Select, asserted low for external data memory access.
26	A14	bidirectional	Address bus bit A14 for external memory accesses; alternately Port A GPIO, with the address bus as the default function after reset.
27	A15	bidirectional	Address bus bit A15 for external memory accesses; alternately Port A GPIO, with the address bus as the default function after reset.
28	VSS	power_in	GND for the internal structures of the chip; all VSS pins should be attached to VSS.
29	WR	output	Write Enable, asserted low during external memory write cycles and can connect directly to the WE pin of a Static RAM.
30	RD	output	Read Enable, asserted low during external memory read cycles and can connect directly to the OE pin of a Static RAM or ROM.
31	IRQA	input	External interrupt request A, a Schmitt-trigger input that can be programmed as level-sensitive or negative-edge-triggered.
32	IRQB	input	External interrupt request B, a Schmitt-trigger input that can be programmed as level-sensitive or negative-edge-triggered.
33	TCS	input	Schmitt pin reserved for factory use that must be tied to VSS for normal use.
34	TCK	input	JTAG/OnCE test clock input, listed as a Schmitt-trigger input; its timing is shown in Figure 3-29.
35	TMS	input	JTAG/OnCE test mode select input, listed as a Schmitt-trigger input.
36	TDI	input	JTAG/OnCE test data input, listed as a Schmitt-trigger input.
37	TDO	output	JTAG/OnCE test data output; its valid-data timing is shown in Figure 3-29.
38	TRST	input	JTAG/OnCE test reset input, listed as a Schmitt-trigger input; its timing is shown in Figure 3-30.
39	VCAPC	passive	Connect to a 2.2 µF or greater bypass capacitor to bypass the core logic voltage regulator, which is required for proper chip operation.
40	ISA0	input	PWM input ISA0, listed as a Schmitt-trigger input.
41	ISA1	input	PWM input ISA1, listed as a Schmitt-trigger input.
42	ISA2	input	PWM input ISA2, listed as a Schmitt-trigger input.
43	FAULTA0	input	PWM fault input used by the fault protection and cycle-by-cycle current limiting of the PWM module.
44	MSCAN_TX	output	CAN transmit output of the CAN interface, which is CAN Version 2.0 A/B-compliant.
45	FAULTA1	input	PWM fault input used by the fault protection and cycle-by-cycle current limiting of the PWM module.
46	MSCAN_RX	input	CAN receive input of the CAN interface, listed as a Schmitt-trigger input.
47	FAULTA2	input	PWM fault input used by the fault protection and cycle-by-cycle current limiting of the PWM module.
48	VREF	power_in	ADC reference pin in the ADC port; its limits are given in Table 2-15, which is not in the provided pages.
49	AN0	input	ADC analog input; with the ADC not sampling, input current is limited to ±15 µA with VIN between VSSA and VDDA.
50	AN1	input	ADC analog input; with the ADC not sampling, input current is limited to ±15 µA with VIN between VSSA and VDDA.
51	AN2	input	ADC analog input; with the ADC not sampling, input current is limited to ±15 µA with VIN between VSSA and VDDA.
52	AN3	input	ADC analog input; with the ADC not sampling, input current is limited to ±15 µA with VIN between VSSA and VDDA.
53	AN4	input	ADC analog input; with the ADC not sampling, input current is limited to ±15 µA with VIN between VSSA and VDDA.
54	AN5	input	ADC analog input; with the ADC not sampling, input current is limited to ±15 µA with VIN between VSSA and VDDA.
55	AN6	input	ADC analog input; with the ADC not sampling, input current is limited to ±15 µA with VIN between VSSA and VDDA.
56	AN7	input	ADC analog input; with the ADC not sampling, input current is limited to ±15 µA with VIN between VSSA and VDDA.
57	XTAL	bidirectional	Crystal oscillator output that should be connected to an 8MHz crystal or ceramic resonator; it can also be driven by an external clock source.
58	EXTAL	input	External crystal oscillator input that should be connected to an 8MHz crystal or ceramic resonator.
59	VSSA	power_in	Analog ground pin for the analog portion of the chip.
60	VDDA	power_in	Dedicated analog power pin that should be connected to a low noise 3.3V supply.
61	VDD	power_in	Provides power to the internal structures of the chip; all VDD pins should be attached to VDD.
62	VDD	power_in	Provides power to the internal structures of the chip; all VDD pins should be attached to VDD.
63	VSS	power_in	GND for the internal structures of the chip; all VSS pins should be attached to VSS.
64	PHASEA0 (TA0)	input	Quadrature decoder phase A input, alternately Quad Timer A pin TA0; the decoder captures all four transitions on the two-phase inputs.
65	PHASEB0 (TA1)	input	Quadrature decoder phase B input, alternately Quad Timer A pin TA1; the decoder captures all four transitions on the two-phase inputs.
66	VDD	power_in	Provides power to the internal structures of the chip; all VDD pins should be attached to VDD.
67	VSS	power_in	GND for the internal structures of the chip; all VSS pins should be attached to VSS.
68	INDEX0 (TA2)	input	Quadrature decoder index input, alternately Quad Timer A pin TA2.
69	HOME0 (TA3)	input	Quadrature decoder home input, alternately Quad Timer A pin TA3.
70	PWMA0	output	PWM output with sufficient drive to directly drive standard opto-isolators; the PWM supports complementary and independent outputs for six PWM outputs in total.
71	PWMA1	output	PWM output with sufficient drive to directly drive standard opto-isolators; the PWM supports complementary and independent outputs for six PWM outputs in total.
72	PWMA2	output	PWM output with sufficient drive to directly drive standard opto-isolators; the PWM supports complementary and independent outputs for six PWM outputs in total.
73	PWMA3	output	PWM output with sufficient drive to directly drive standard opto-isolators; the PWM supports complementary and independent outputs for six PWM outputs in total.
74	PWMA4	output	PWM output with sufficient drive to directly drive standard opto-isolators; the PWM supports complementary and independent outputs for six PWM outputs in total.
75	PWMA5	output	PWM output with sufficient drive to directly drive standard opto-isolators; the PWM supports complementary and independent outputs for six PWM outputs in total.
76	TXD0 (GPIOE0)	output	SCI0 transmit data output, alternately Port E GPIO.
77	RXD0 (GPIOE1)	input	SCI0 receive data input, alternately Port E GPIO.
78	EXTBOOT	input	Schmitt-trigger input listed in the Table 3-4 notes; its full function is in the Table 2-9 continuation, which is not in the provided pages.
79	RESET	input	Schmitt-trigger input listed in the Table 3-4 notes; its full function is in the Table 2-9 continuation, which is not in the provided pages.
80	DE	bidirectional	JTAG/OnCE port signal whose timing is shown in Figure 3-31 (debug event); full function is in Table 2-17, not in the provided pages.
81	CLKO	output	Buffered clock output whose source is selected by CLKOSEL[4:0] in CLKOSR, or which can be disabled by that register.
82	TD1	bidirectional	Quad Timer D pin, part of the Quad Timer module port; its limits are in Table 2-16, not in the provided pages.
83	TD2	bidirectional	Quad Timer D pin, part of the Quad Timer module port; its limits are in Table 2-16, not in the provided pages.
84	SS (GPIOE7)	bidirectional	SPI slave select, alternately Port E GPIO; the SPI port can be used as GPIO if SPI is not required.
85	MISO (GPIOE6)	bidirectional	SPI master-in/slave-out data pin, alternately Port E GPIO; the SPI port can be used as GPIO if SPI is not required.
86	MOSI (GPIOE5)	bidirectional	SPI master-out/slave-in data pin, alternately Port E GPIO; the SPI port can be used as GPIO if SPI is not required.
87	SCLK (GPIOE4)	bidirectional	SPI serial clock pin, alternately Port E GPIO; the SPI port can be used as GPIO if SPI is not required.
88	VCAPC	passive	Connect to a 2.2 µF or greater bypass capacitor to bypass the core logic voltage regulator, which is required for proper chip operation.
89	D0	bidirectional	External data bus bit D0, tri-stated when the external bus is inactive and internal pull-ups may be active.
90	D1	bidirectional	External data bus bit D1, tri-stated when the external bus is inactive and internal pull-ups may be active.
91	D2	bidirectional	External data bus bit D2, tri-stated when the external bus is inactive and internal pull-ups may be active.
92	VDD	power_in	Provides power to the internal structures of the chip; all VDD pins should be attached to VDD.
93	VSS	power_in	GND for the internal structures of the chip; all VSS pins should be attached to VSS.
94	D3	bidirectional	External data bus bit D3, tri-stated when the external bus is inactive and internal pull-ups may be active.
95	D4	bidirectional	External data bus bit D4, tri-stated when the external bus is inactive and internal pull-ups may be active.
96	D5	bidirectional	External data bus bit D5, tri-stated when the external bus is inactive and internal pull-ups may be active.
97	D6	bidirectional	External data bus bit D6, tri-stated when the external bus is inactive and internal pull-ups may be active.
98	D7	bidirectional	External data bus bit D7, tri-stated when the external bus is inactive and internal pull-ups may be active.
99	D8	bidirectional	External data bus bit D8, tri-stated when the external bus is inactive and internal pull-ups may be active.
100	D9	bidirectional	External data bus bit D9, tri-stated when the external bus is inactive and internal pull-ups may be active.

Key specifications

Parameter	Value
Manufacturer	NXP Semicon
Package	LQFP-100(14x14)
Category	Embedded Processors & Controllers
Pins	100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage, digital	VDD	3	3.3	3.6	V		23
Supply voltage, analog	VDDA	3	3.3	3.6	V		23
Voltage difference VDD to VDDA	ΔVDD	-0.1		0.1	V		23
Voltage difference VSS to VSSA	ΔVSS	-0.1		0.1	V		24
ADC reference voltage	VREF	2.7			V	Max printed as VDDA	24
Ambient operating temperature	TA	-40		85	°C		24
Supply voltage (absolute maximum)	VDD	-0.3		4	V	Printed as VSS, 0.3 V (min) and VSS + 4.0 V (max)	23
All other input voltages, excluding analog inputs	VIN	-0.3		5.5	V	Printed as VSS, 0.3 V (min) and VSS + 5.5 V (max)	23
Voltage difference VDD to VDDA (absolute maximum)	ΔVDD	-0.3		0.3	V		23
Voltage difference VSS to VSSA (absolute maximum)	ΔVSS	-0.3		0.3	V		23
Current drain per pin excluding VDD, VSS, PWM outputs, TCS, VPP, VDDA, VSSA	I			10	mA		23
Analog inputs EXTAL and XTAL	VIN	-0.3		3	V	Printed as VSSA, 0.3 V (min) and VSSA + 3.0 V (max)	23
Analog inputs ANA0-7 and VREF	VIN	-0.3			V	Printed as VSSA, 0.3 V (min) and VDDA + 0.3 V (max)	23
Input high voltage (XTAL/EXTAL)	VIHC	2.25		2.75	V		25
Input low voltage (XTAL/EXTAL)	VILC	0		0.5	V		25
Input high voltage (Schmitt trigger inputs)	VIHS	2.2		5.5	V		25
Input low voltage (Schmitt trigger inputs)	VILS	-0.3		0.8	V		25
Input high voltage (all other digital inputs)	VIH	2		5.5	V		25
Input low voltage (all other digital inputs)	VIL	-0.3		0.8	V		25
Input current high	IIH	-1		1	μA	Pullup/pulldown resistors disabled, VIN=VDD	25
Input current low	IIL	-1		1	μA	Pullup/pulldown resistors disabled, VIN=VSS	25
Input current high (with pullup resistor)	IIHPU	-1		1	μA	With pullup resistor, VIN=VDD	25
Input current low (with pullup resistor)	IILPU	-210		-50	μA	With pullup resistor, VIN=VSS	25
Input current high (with pulldown resistor)	IIHPD	20		180	μA	With pulldown resistor, VIN=VDD	25
Input current low (with pulldown resistor)	IILPD	-1		1	μA	With pulldown resistor, VIN=VSS	25
Output tri-state current low	IOZL	-10		10	μA		25
Output tri-state current high	IOZH	-10		10	μA		25
Input current high (analog inputs)	IIHA	-15		15	μA	VIN=VDDA	26
Input current low (analog inputs)	IILA	-15		15	μA	VIN=VSSA	26
Output Low Voltage	VOL			0.4	V	At IOL	26
Output source current	IOH	4			mA		26
Output sink current	IOL	4			mA		26
PWM pin output source current	IOHP	10			mA	50% duty cycle	26
PWM pin output sink current	IOLP	16			mA	50% duty cycle	26
VDD supply current, Run	IDDT		126	152	mA	Run; 8 MHz clock source; outputs unloaded	26
VDD supply current, Wait	IDDT		105	129	mA	Wait; external 8 MHz square-wave clock source	26
VDD supply current, Stop	IDDT		60	84	mA	Stop	26
Low Voltage Interrupt, external power supply	VEIO	2.4	2.7	3	V		26
Low Voltage Interrupt, internal power supply	VEIC	2	2.2	2.4	V		26
Power on Reset	VPOR		1.7	2	V		26
Resolution	RES	12		12	Bits		48
Integral Non-Linearity	INL	-4	2.5	4	LSB		48
Differential Non-Linearity	DNL	-1	0.9	1	LSB		48
Gain Error (transfer gain)	EGAIN	0.95	1	1.1			48
Offset Voltage	VOFFSET	-80	-15	20	mV		48
ADC internal clock	fADIC	0.5		5	MHz		48
VREF Quiescent Current (both ADCs)	IVREF		12	16.5	mA		49
External clock frequency of operation	fosc	0		80	MHz	External clock driver	34
Clock pulse width	tPW	6.25			ns		34
External reference crystal frequency for the PLL	fosc	4	8	10	MHz		35
PLL output frequency	fout/2	40		110	MHz		35
PLL stabilization time	tplls		1	10	ms	0 to +85 °C	35
Program time	Tprog	20			us		29
Erase time	Terase	20			ms		29
Mass erase time	Tme	100			ms		29
Endurance	ECYC	10000	20000		cycles		29
Data Retention	DRET	10	30		years		29
Junction to ambient, natural convection	RθJA		41.7		°C/W	Natural convection	24
Junction to ambient (@1m/sec)	RθJMA		37.2		°C/W	@1m/sec	24
Junction to case	RθJC		10.2		°C/W		24

CAD (KiCad official)

Symbol: DSP56F803BU80E
Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
3D model files: dsp56f803bu80e-etched.step / dsp56f803bu80e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dsp56f803bu80e.step / dsp56f803bu80e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: NXP Semicon datasheet (57 pp, sha256 ff676f1917189cb5, retrieved 2026-10-30, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

DSP56F803BU80E

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3D Model

Symbol & Footprint

Schematic Symbol

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Datasheet

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