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DS92LV18TVV

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Texas Instruments Serializers / Deserializers, LQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DS92LV18TVV

Texas Instruments · Serializers / Deserializers · LQFP-80(12x12)

DS92LV18TVV from Texas Instruments, in a LQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RPWDN input Driving RPWDN low puts the receiver in low-power standby mode and the receiver PLL loses lock.
2 REN input REN low disables the receiver outputs while the receiver PLL remains locked.
3 DIN17 input Transmitter parallel data input bit 17, strobed by TCLK and ignored when SYNC is high.
4 REFCLK input Frequency reference clock input for the receiver, which must be running for the deserializer to lock to incoming data.
5 AVDD power_in Analog voltage supply for the LVDS section of the device.
6 AGND power_in Analog ground for the LVDS section, connected to signal common in the cable for common-mode return.
7 RIN+ input Receiver LVDS true serial input.
8 RIN- input Receiver LVDS inverting serial input.
9 AGND power_in Analog ground for the LVDS section, connected to signal common in the cable for common-mode return.
10 AVDD power_in Analog voltage supply for the LVDS section of the device.
11 AVDD power_in Analog voltage supply for the LVDS section of the device.
12 AGND power_in Analog ground for the LVDS section, connected to signal common in the cable for common-mode return.
13 DO+ output Transmitter LVDS true serial output, disabled during local loopback and tri-stated when DEN is low.
14 DO- output Transmitter LVDS inverting serial output, disabled during local loopback and tri-stated when DEN is low.
15 AVDD power_in Analog voltage supply for the LVDS section of the device.
16 AGND power_in Analog ground for the LVDS section, connected to signal common in the cable for common-mode return.
17 TCLK input Transmitter reference clock used to strobe DIN inputs and drive the transmitter PLL.
18 DIN16 input Transmitter parallel data input bit 16, strobed by TCLK and ignored when SYNC is high.
19 DEN input DEN low disables the transmitter outputs while the transmitter PLL remains locked.
20 SYNC input SYNC high makes the transmitter ignore data inputs and send SYNC patterns to provide a locking reference to the receiver.
21 DIN input Transmitter parallel data input, strobed by TCLK and ignored when SYNC is high.
22 DIN input Transmitter parallel data input, strobed by TCLK and ignored when SYNC is high.
23 DIN input Transmitter parallel data input, strobed by TCLK and ignored when SYNC is high.
24 DIN input Transmitter parallel data input, strobed by TCLK and ignored when SYNC is high.
25 DIN input Transmitter parallel data input, strobed by TCLK and ignored when SYNC is high.
26 DIN input Transmitter parallel data input, strobed by TCLK and ignored when SYNC is high.
27 DIN input Transmitter parallel data input, strobed by TCLK and ignored when SYNC is high.
28 DIN input Transmitter parallel data input, strobed by TCLK and ignored when SYNC is high.
29 PGND power_in PLL ground for the transmitter and receiver PLL circuits.
30 PVDD power_in PLL voltage supply, which requires clean power to minimize jitter.
31 PVDD power_in PLL voltage supply, which requires clean power to minimize jitter.
32 PGND power_in PLL ground for the transmitter and receiver PLL circuits.
33 DIN input Transmitter parallel data input, strobed by TCLK and ignored when SYNC is high.
34 DIN input Transmitter parallel data input, strobed by TCLK and ignored when SYNC is high.
35 DIN input Transmitter parallel data input, strobed by TCLK and ignored when SYNC is high.
36 DIN input Transmitter parallel data input, strobed by TCLK and ignored when SYNC is high.
37 DIN input Transmitter parallel data input, strobed by TCLK and ignored when SYNC is high.
38 DIN input Transmitter parallel data input, strobed by TCLK and ignored when SYNC is high.
39 DIN input Transmitter parallel data input, strobed by TCLK and ignored when SYNC is high.
40 DIN input Transmitter parallel data input, strobed by TCLK and ignored when SYNC is high.
41 DGND power_in Digital ground for the device and receiver output buffers.
42 TPWDN input TPWDN low puts the transmitter in low-power standby mode and the transmitter PLL loses lock.
43 DVDD power_in Digital voltage supply for the device and receiver output buffers, requiring local bypass of 0.1uF per pin.
44 DGND power_in Digital ground for the device and receiver output buffers.
45 ROUT output Receiver parallel data output, asserted HIGH on failsafe and tri-stated when REN is low.
46 ROUT output Receiver parallel data output, asserted HIGH on failsafe and tri-stated when REN is low.
47 ROUT output Receiver parallel data output, asserted HIGH on failsafe and tri-stated when REN is low.
48 ROUT output Receiver parallel data output, asserted HIGH on failsafe and tri-stated when REN is low.
49 RCLK output Recovered parallel-rate LVCMOS clock used to strobe ROUT(0:17), asserted HIGH on failsafe.
50 DVDD power_in Digital voltage supply for the device and receiver output buffers, requiring local bypass of 0.1uF per pin.
51 DGND power_in Digital ground for the device and receiver output buffers.
52 DGND power_in Digital ground for the device and receiver output buffers.
53 DVDD power_in Digital voltage supply for the device and receiver output buffers, requiring local bypass of 0.1uF per pin.
54 ROUT output Receiver parallel data output, asserted HIGH on failsafe and tri-stated when REN is low.
55 ROUT output Receiver parallel data output, asserted HIGH on failsafe and tri-stated when REN is low.
56 ROUT output Receiver parallel data output, asserted HIGH on failsafe and tri-stated when REN is low.
57 ROUT output Receiver parallel data output, asserted HIGH on failsafe and tri-stated when REN is low.
58 DVDD power_in Digital voltage supply for the device and receiver output buffers, requiring local bypass of 0.1uF per pin.
59 DGND power_in Digital ground for the device and receiver output buffers.
60 DGND power_in Digital ground for the device and receiver output buffers.
61 DGND power_in Digital ground for the device and receiver output buffers.
62 ROUT16 output Receiver parallel data output bit 16, asserted HIGH on failsafe and tri-stated when REN is low.
63 LOCK output Receiver PLL status output, high when the receiver PLL is unlocked and low when locked.
64 ROUT output Receiver parallel data output, asserted HIGH on failsafe and tri-stated when REN is low.
65 ROUT output Receiver parallel data output, asserted HIGH on failsafe and tri-stated when REN is low.
66 ROUT output Receiver parallel data output, asserted HIGH on failsafe and tri-stated when REN is low.
67 ROUT output Receiver parallel data output, asserted HIGH on failsafe and tri-stated when REN is low.
68 DGND power_in Digital ground for the device and receiver output buffers.
69 DVDD power_in Digital voltage supply for the device and receiver output buffers, requiring local bypass of 0.1uF per pin.
70 ROUT output Receiver parallel data output, asserted HIGH on failsafe and tri-stated when REN is low.
71 ROUT output Receiver parallel data output, asserted HIGH on failsafe and tri-stated when REN is low.
72 ROUT output Receiver parallel data output, asserted HIGH on failsafe and tri-stated when REN is low.
73 ROUT output Receiver parallel data output, asserted HIGH on failsafe and tri-stated when REN is low.
74 PGND power_in PLL ground for the transmitter and receiver PLL circuits.
75 PVDD power_in PLL voltage supply, which requires clean power to minimize jitter.
76 PGND power_in PLL ground for the transmitter and receiver PLL circuits.
77 PVDD power_in PLL voltage supply, which requires clean power to minimize jitter.
78 LINE_LE input LINE_LE high enables receiver loopback, feeding RIN± data back through the DO± outputs.
79 LOCAL_LE input LOCAL_LE high enables transmitter loopback, feeding DIN data back through the ROUT outputs.
80 ROUT17 output Receiver parallel data output bit 17, asserted HIGH on failsafe and tri-stated when REN is low.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-80(12x12)
Category Interface ICs
Pins 80

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage (VCC) VCC -0.3 4 V 2
LVCMOS/LVTTL Input Voltage -0.3 V max (VCC +0.3V) 2
LVCMOS/LVTTL Output Voltage -0.3 V max (VCC +0.3V) 2
Bus LVDS Receiver Input Voltage -0.3 3.9 V 2
Bus LVDS Driver Output Voltage -0.3 3.9 V 2
Bus LVDS Output Short Circuit Duration 10 ms 2
Junction Temperature 150 °C 2
Storage Temperature -65 150 °C 2
Lead Temperature (Soldering) 260 °C Soldering, 4 seconds 2
ESD Rating (HBM) 2 kV HBM, printed as >2.0kV 2
Thermal resistance junction-to-ambient θJA 43 °C/W 80L LQFP 2
Thermal resistance junction-to-case θJC 11.1 °C/W 80L LQFP 2
Supply Voltage (VCC) VCC 3.15 3.3 3.45 V 2
Operating Free Air Temperature (TA) TA -40 25 85 °C 2
Clock Rate 15 66 MHz 2
Supply Noise 100 mV (p-p) 2
High Level Input Voltage VIH 2 V DEN, TCLK, TPWDN, SYNC, RCLK_R/F, REN, REFCLK 3
Low Level Input Voltage VIL 0.8 V DIN, GND 3
Input Clamp Voltage VCL -1.5 -0.7 V ICL = −18 mA 3
RPWDN Input Current IIN -10 10 μA VIN = 0V or 3.6V 3
High Level Output Voltage VOH 2.3 3 V IOH = −9 mA 3
Low Level Output Voltage VOL 0.33 0.5 V IOL = 9 mA, ROUT, RCLK, LOCK, GND 3
Output Short Circuit Current IOS -15 -48 -85 mA VOUT = 0V 3
TRI-STATE Output Current IOZ -10 0.4 10 μA PWRDN or REN = 0.8V, VOUT = 0V or VCC, ROUT, RCLK 3
Differential Threshold High Voltage VTH 100 mV VCM = +1.1V 3
Differential Threshold Low Voltage VTL -100 mV VCM = +1.1V 3
Input Current RI+, RI- IIN -10 10 μA VIN = +2.4V, VCC = 3.6V or 0V 3
Output Differential Voltage VOD 350 500 550 mV Figure 19, RL = 100Ω 3
Output Differential Voltage Unbalance ΔVOD 2 15 mV 3
Offset Voltage VOS 1.05 1.2 1.25 V 3
Offset Voltage Unbalance ΔVOS 2.7 15 mV 3
Driver Output Short Circuit Current IOS -35 -50 -70 mA DO = 0V, Din = H, DO+, DO- = 2.4V, TPWDN and DEN 3
Driver TRI-STATE Output Current IOZ -10 1 10 µA TPWDN or DEN = 0.8V, DO = 0V OR VDD = 3.6V 3
Power-Off Output Current IOX -10 1 10 µA VDD = 0V, DO = 0V or 3.6V 3
Serializer supply current (PRBS-15) 190 mA CL = 15pF, f = 66 MHz, PRBS-15 pattern, RL = 100 Ω 3
Total Supply Current (worst case) ICCT 220 320 mA f = 66 MHz, CL = 15 pF, RL = 100 Ω, checker-board pattern 3
Supply Current Powerdown ICCX 1.5 3 mA PWRDN = 0.8V, REN = 0.8V 3
Transmit Clock Period tTCP 15.2 66.7 ns 4
TCLK Input Transition Time tCLKT 3 6 ns 4
REFCLK Period tRFCP 15.2 66.7 ns 4
REFCLK Duty Cycle tRFDC 40 50 60 % 4
Ratio of REFCLK to TCLK tRFCP / tTCP 0.95 1.05 4
REFCLK Transition Time tRFTT 6 ns 4
Receiver out Clock Period tRCP 15.2 66.7 ns tRCP = tTCP 5
RCLK Duty Cycle tRDC 45 50 55 % RCLK 5

CAD (KiCad official)

  • Symbol: DS92LV18TVV
  • Footprint: Package_QFP:LQFP-80_12x12mm_P0.5mm
  • 3D model: LQFP-80(12x12) (KiCad packages3D, STEP)
  • 3D model files: ds92lv18tvv-etched.step / ds92lv18tvv-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds92lv18tvv.step / ds92lv18tvv.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (29 pp, sha256 006330896207a53d, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF