DS90UR124QVSX

{
  "slug": "ds90ur124qvsx",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments LVDS ICs, TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "interface",
    "ds90ur124qvsx",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "ds90ur124qvsx.kicad_sym",
    "ds90ur124qvsx.kicad_mod",
    "ds90ur124qvsx.glb",
    "ds90ur124qvsx.step",
    "ds90ur124qvsx.lbr",
    "docs/hero.png",
    "docs/ds90ur124qvsx-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "ds90ur124qvsx-hero.glb",
    "ds90ur124qvsx-hero.overlay.json",
    "ds90ur124qvsx-etched.glb"
  ],
  "component": {
    "mpn": "DS90UR124QVSX",
    "manufacturer": "Texas Instruments",
    "package": "TQFP-64(10x10)",
    "pin_count": 64,
    "category": "Interface",
    "subcategory": "LVDS ICs",
    "datasheet": "https://www.ti.com/lit/ds/symlink/ds90ur124.pdf",
    "parts": {
      "symbol": "ds90ur124qvsx.kicad_sym",
      "footprint": "ds90ur124qvsx.kicad_mod",
      "model_3d": "ds90ur124qvsx-hero.glb",
      "model_3d_plain": "ds90ur124qvsx-etched.glb",
      "model_3d_step": "ds90ur124qvsx-etched.step",
      "model_3d_step_plain": "ds90ur124qvsx.step",
      "lbr": "ds90ur124qvsx.lbr"
    },
    "distributor_links": {
      "lcsc": "C527465",
      "digikey": "296-35247-2-ND",
      "mouser": "926-DS90UR124QVSXNPB"
    },
    "distributor_check": {
      "checked_at": "2026-11-11T01:41:14Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "296-35247-2-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "926-DS90UR124QVSXNPB",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "RES0",
        "type": "unconnected",
        "description": "No connection, not physically connected to the die; leave open or tie LOW."
      },
      {
        "number": "2",
        "name": "RES0",
        "type": "unconnected",
        "description": "No connection, not physically connected to the die; leave open or tie LOW."
      },
      {
        "number": "3",
        "name": "RES0",
        "type": "unconnected",
        "description": "No connection, not physically connected to the die; leave open or tie LOW."
      },
      {
        "number": "4",
        "name": "RES0",
        "type": "unconnected",
        "description": "No connection, not physically connected to the die; leave open or tie LOW."
      },
      {
        "number": "5",
        "name": "RES0",
        "type": "unconnected",
        "description": "No connection, not physically connected to the die; leave open or tie LOW."
      },
      {
        "number": "6",
        "name": "RES0",
        "type": "unconnected",
        "description": "No connection, not physically connected to the die; leave open or tie LOW."
      },
      {
        "number": "7",
        "name": "ROUT[23]",
        "type": "output",
        "description": "LVCMOS receiver parallel data output, Group 3 (ROUT[23:16]); tri-stated when LOCK is low."
      },
      {
        "number": "8",
        "name": "ROUT[22]",
        "type": "output",
        "description": "LVCMOS receiver parallel data output, Group 3 (ROUT[23:16]); tri-stated when LOCK is low."
      },
      {
        "number": "9",
        "name": "ROUT[21]",
        "type": "output",
        "description": "LVCMOS receiver parallel data output, Group 3 (ROUT[23:16]); tri-stated when LOCK is low."
      },
      {
        "number": "10",
        "name": "ROUT[20]",
        "type": "output",
        "description": "LVCMOS receiver parallel data output, Group 3 (ROUT[23:16]); tri-stated when LOCK is low."
      },
      {
        "number": "11",
        "name": "VDD",
        "type": "power_in",
        "description": "Digital voltage supply for the LVCMOS outputs, 3.0V to 3.6V (3.3V nominal)."
      },
      {
        "number": "12",
        "name": "VSS",
        "type": "power_in",
        "description": "Digital ground for the LVCMOS outputs."
      },
      {
        "number": "13",
        "name": "ROUT[19]",
        "type": "output",
        "description": "LVCMOS receiver parallel data output, Group 3 (ROUT[23:16]); tri-stated when LOCK is low."
      },
      {
        "number": "14",
        "name": "ROUT[18]",
        "type": "output",
        "description": "LVCMOS receiver parallel data output, Group 3 (ROUT[23:16]); tri-stated when LOCK is low."
      },
      {
        "number": "15",
        "name": "ROUT[17]",
        "type": "output",
        "description": "LVCMOS receiver parallel data output, Group 3 (ROUT[23:16]); tri-stated when LOCK is low."
      },
      {
        "number": "16",
        "name": "ROUT[16]",
        "type": "output",
        "description": "LVCMOS receiver parallel data output, Group 3 (ROUT[23:16]); tri-stated when LOCK is low."
      },
      {
        "number": "17",
        "name": "RES0",
        "type": "unconnected",
        "description": "No connection, not physically connected to the die; leave open or tie LOW."
      },
      {
        "number": "18",
        "name": "RES0",
        "type": "unconnected",
        "description": "No connection, not physically connected to the die; leave open or tie LOW."
      },
      {
        "number": "19",
        "name": "ROUT[15]",
        "type": "output",
        "description": "LVCMOS receiver parallel data output, Group 2 (ROUT[15:8]); tri-stated when LOCK is low."
      },
      {
        "number": "20",
        "name": "ROUT[14]",
        "type": "output",
        "description": "LVCMOS receiver parallel data output, Group 2 (ROUT[15:8]); tri-stated when LOCK is low."
      },
      {
        "number": "21",
        "name": "ROUT[13]",
        "type": "output",
        "description": "LVCMOS receiver parallel data output, Group 2 (ROUT[15:8]); tri-stated when LOCK is low."
      },
      {
        "number": "22",
        "name": "ROUT[12]",
        "type": "output",
        "description": "LVCMOS receiver parallel data output, Group 2 (ROUT[15:8]); tri-stated when LOCK is low."
      },
      {
        "number": "23",
        "name": "LOCK",
        "type": "output",
        "description": "Receiver PLL status: H = PLL locked; L = unlocked, with ROUT[23:0] and RCLK tri-stated."
      },
      {
        "number": "24",
        "name": "RCLK",
        "type": "output",
        "description": "LVCMOS parallel interface clock output; strobe edge set by the RRFB pin."
      },
      {
        "number": "25",
        "name": "VSS",
        "type": "power_in",
        "description": "Digital ground for the LVCMOS outputs."
      },
      {
        "number": "26",
        "name": "VDD",
        "type": "power_in",
        "description": "Digital voltage supply for the LVCMOS outputs, 3.0V to 3.6V (3.3V nominal)."
      },
      {
        "number": "27",
        "name": "ROUT[11]",
        "type": "output",
        "description": "LVCMOS receiver parallel data output, Group 2 (ROUT[15:8]); tri-stated when LOCK is low."
      },
      {
        "number": "28",
        "name": "ROUT[10]",
        "type": "output",
        "description": "LVCMOS receiver parallel data output, Group 2 (ROUT[15:8]); tri-stated when LOCK is low."
      },
      {
        "number": "29",
        "name": "ROUT[9]",
        "type": "output",
        "description": "LVCMOS receiver parallel data output, Group 2 (ROUT[15:8]); tri-stated when LOCK is low."
      },
      {
        "number": "30",
        "name": "ROUT[8]",
        "type": "output",
        "description": "LVCMOS receiver parallel data output, Group 2 (ROUT[15:8]); tri-stated when LOCK is low."
      },
      {
        "number": "31",
        "name": "VSS",
        "type": "power_in",
        "description": "Digital ground for the logic."
      },
      {
        "number": "32",
        "name": "VDD",
        "type": "power_in",
        "description": "Digital voltage supply for the logic, 3.0V to 3.6V (3.3V nominal)."
      },
      {
        "number": "33",
        "name": "RES0",
        "type": "unconnected",
        "description": "No connection, not physically connected to the die; leave open or tie LOW."
      },
      {
        "number": "34",
        "name": "RES0",
        "type": "unconnected",
        "description": "No connection, not physically connected to the die; leave open or tie LOW."
      },
      {
        "number": "35",
        "name": "ROUT[7]",
        "type": "output",
        "description": "LVCMOS receiver parallel data output, Group 1 (ROUT[7:0]); also carries the BIST error count when BISTM = H."
      },
      {
        "number": "36",
        "name": "ROUT[6]",
        "type": "output",
        "description": "LVCMOS receiver parallel data output, Group 1 (ROUT[7:0]); also carries the BIST error count when BISTM = H."
      },
      {
        "number": "37",
        "name": "ROUT[5]",
        "type": "output",
        "description": "LVCMOS receiver parallel data output, Group 1 (ROUT[7:0]); also carries the BIST error count when BISTM = H."
      },
      {
        "number": "38",
        "name": "ROUT[4]",
        "type": "output",
        "description": "LVCMOS receiver parallel data output, Group 1 (ROUT[7:0]); also carries the BIST error count when BISTM = H."
      },
      {
        "number": "39",
        "name": "VSS",
        "type": "power_in",
        "description": "Digital ground for the LVCMOS outputs."
      },
      {
        "number": "40",
        "name": "VDD",
        "type": "power_in",
        "description": "Digital voltage supply for the LVCMOS outputs, 3.0V to 3.6V (3.3V nominal)."
      },
      {
        "number": "41",
        "name": "ROUT[3]",
        "type": "output",
        "description": "LVCMOS receiver parallel data output, Group 1 (ROUT[7:0]); also carries the BIST error count when BISTM = H."
      },
      {
        "number": "42",
        "name": "ROUT[2]",
        "type": "output",
        "description": "LVCMOS receiver parallel data output, Group 1 (ROUT[7:0]); also carries the BIST error count when BISTM = H."
      },
      {
        "number": "43",
        "name": "ROUT[1]",
        "type": "output",
        "description": "LVCMOS receiver parallel data output, Group 1 (ROUT[7:0]); also carries the BIST error count when BISTM = H."
      },
      {
        "number": "44",
        "name": "ROUT[0]",
        "type": "output",
        "description": "LVCMOS receiver parallel data output, Group 1 (ROUT[7:0]); also carries the BIST error count when BISTM = H."
      },
      {
        "number": "45",
        "name": "PASS",
        "type": "output",
        "description": "@Speed BIST pass flag: L = BIST failure; H = 1x10-9 error rate achieved across the link (LOCK must be H before BIST is enabled)."
      },
      {
        "number": "46",
        "name": "VDD",
        "type": "power_in",
        "description": "Digital voltage supply for the logic, 3.0V to 3.6V (3.3V nominal)."
      },
      {
        "number": "47",
        "name": "VSS",
        "type": "power_in",
        "description": "Digital ground for the logic."
      },
      {
        "number": "48",
        "name": "RPWDNB",
        "type": "input",
        "description": "Receiver power down bar: H = receiver enabled; L = power-down, with ROUT[23:0], RCLK and LOCK tri-stated and the PLL shut down."
      },
      {
        "number": "49",
        "name": "PTOSEL",
        "type": "input",
        "description": "Progressive Turn On selection: H = ROUT in three groups of eight, about ±1 UI to ±2 UI apart relative to RCLK; L = PTO spread mode."
      },
      {
        "number": "50",
        "name": "RES0",
        "type": "input",
        "description": "Reserved; this pin must be tied LOW."
      },
      {
        "number": "51",
        "name": "VDD",
        "type": "power_in",
        "description": "Analog LVDS voltage supply, 3.0V to 3.6V (3.3V nominal)."
      },
      {
        "number": "52",
        "name": "VSS",
        "type": "power_in",
        "description": "Analog LVDS ground."
      },
      {
        "number": "53",
        "name": "RIN+",
        "type": "input",
        "description": "Receiver LVDS true (+) input; terminate with 100Ω across RIN+/RIN- and AC-couple with a 100nF capacitor."
      },
      {
        "number": "54",
        "name": "RIN-",
        "type": "input",
        "description": "Receiver LVDS inverted (-) input; terminate with 100Ω across RIN+/RIN- and AC-couple with a 100nF capacitor."
      },
      {
        "number": "55",
        "name": "RRFB",
        "type": "input",
        "description": "Receiver clock edge select: H = ROUT strobed on the rising RCLK edge; L = falling edge."
      },
      {
        "number": "56",
        "name": "VSS",
        "type": "power_in",
        "description": "Analog ground for the PLL VCO."
      },
      {
        "number": "57",
        "name": "VDD",
        "type": "power_in",
        "description": "Analog voltage supply for the PLL VCO, 3.0V to 3.6V (3.3V nominal)."
      },
      {
        "number": "58",
        "name": "VSS",
        "type": "power_in",
        "description": "Analog ground for the PLL."
      },
      {
        "number": "59",
        "name": "VDD",
        "type": "power_in",
        "description": "Analog voltage supply for the PLL, 3.0V to 3.6V (3.3V nominal)."
      },
      {
        "number": "60",
        "name": "REN",
        "type": "input",
        "description": "Receiver data enable: H = ROUT[23:0] and RCLK enabled; L = they are disabled (tri-state) while the PLL stays locked."
      },
      {
        "number": "61",
        "name": "BISTEN",
        "type": "input",
        "description": "BIST mode enable: L = normal mode (default); H = BIST mode active, with status on the PASS pin."
      },
      {
        "number": "62",
        "name": "BISTM",
        "type": "input",
        "description": "BIST mode select: L = per-bit error status on ROUT (default); H = accumulated error count (up to 255) on ROUT[7:0]."
      },
      {
        "number": "63",
        "name": "RAOFF",
        "type": "input",
        "description": "Randomizer control: H = backwards compatible mode for use with the DS90C241 serializer; L = additional randomization ON (default)."
      },
      {
        "number": "64",
        "name": "SLEW",
        "type": "input",
        "description": "LVCMOS output slew rate control: L = low drive output at 2mA (default); H = high drive output at 4mA."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Datasheet gives the pin range ROUT[23:16] (pins 7-10 and 13-16) but the bit-to-pin assignment within; Table 4-2 gives ROUT[7:0] on pins 35-38 and 41-44 without a per-bit mapping; the bit order was taken; ROUT[15:8] per-bit mapping was taken from the Figure 4-2 sequence; it agrees with the table's LOCK ("
        ],
        "pages_sent": 45,
        "cost_usd": 0.2608,
        "at": "2026-11-11T01:40:53"
      },
      "datasheet": {
        "url": "https://www.ti.com/lit/ds/symlink/ds90ur124.pdf",
        "pages": 45,
        "sha256": "fbb642ca8b1cda5a",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 64,
        "described": 64,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "ds90ur124qvsx.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          12.0,
          12.0,
          1.1
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "60567e81b0770b6c519104183a7a05ba52dddc11146b5fbe21434fbb5801696c",
        "checked": "2026-11-11",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "ds90ur124qvsx-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          12.0,
          12.0,
          1.1
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "e03e3741c01cd654e1cca3d8e5166d380e3fe087cba87e82b0d8bbd73c40d2f3",
        "checked": "2026-11-11",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ],
    "package_dims": {
      "package_code": "PAG",
      "source_page": 41,
      "e": {
        "nom_mm": 0.5,
        "range_mm": [
          null,
          null
        ]
      },
      "A": {
        "nom_mm": 1.2,
        "range_mm": [
          null,
          1.2
        ]
      },
      "source": "datasheet package drawing, every number found on its page (extract_pins --task dims)",
      "model_check": {
        "file": "ds90ur124qvsx.step",
        "verdict": "PASS",
        "reasons": [
          "height within the datasheet's package drawing"
        ],
        "by": "factory/package_fit.py"
      }
    }
  }
}