DS90UR124QVSX from Texas Instruments, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	RES0	unconnected	No connection, not physically connected to the die; leave open or tie LOW.
2	RES0	unconnected	No connection, not physically connected to the die; leave open or tie LOW.
3	RES0	unconnected	No connection, not physically connected to the die; leave open or tie LOW.
4	RES0	unconnected	No connection, not physically connected to the die; leave open or tie LOW.
5	RES0	unconnected	No connection, not physically connected to the die; leave open or tie LOW.
6	RES0	unconnected	No connection, not physically connected to the die; leave open or tie LOW.
7	ROUT[23]	output	LVCMOS receiver parallel data output, Group 3 (ROUT[23:16]); tri-stated when LOCK is low.
8	ROUT[22]	output	LVCMOS receiver parallel data output, Group 3 (ROUT[23:16]); tri-stated when LOCK is low.
9	ROUT[21]	output	LVCMOS receiver parallel data output, Group 3 (ROUT[23:16]); tri-stated when LOCK is low.
10	ROUT[20]	output	LVCMOS receiver parallel data output, Group 3 (ROUT[23:16]); tri-stated when LOCK is low.
11	VDD	power_in	Digital voltage supply for the LVCMOS outputs, 3.0V to 3.6V (3.3V nominal).
12	VSS	power_in	Digital ground for the LVCMOS outputs.
13	ROUT[19]	output	LVCMOS receiver parallel data output, Group 3 (ROUT[23:16]); tri-stated when LOCK is low.
14	ROUT[18]	output	LVCMOS receiver parallel data output, Group 3 (ROUT[23:16]); tri-stated when LOCK is low.
15	ROUT[17]	output	LVCMOS receiver parallel data output, Group 3 (ROUT[23:16]); tri-stated when LOCK is low.
16	ROUT[16]	output	LVCMOS receiver parallel data output, Group 3 (ROUT[23:16]); tri-stated when LOCK is low.
17	RES0	unconnected	No connection, not physically connected to the die; leave open or tie LOW.
18	RES0	unconnected	No connection, not physically connected to the die; leave open or tie LOW.
19	ROUT[15]	output	LVCMOS receiver parallel data output, Group 2 (ROUT[15:8]); tri-stated when LOCK is low.
20	ROUT[14]	output	LVCMOS receiver parallel data output, Group 2 (ROUT[15:8]); tri-stated when LOCK is low.
21	ROUT[13]	output	LVCMOS receiver parallel data output, Group 2 (ROUT[15:8]); tri-stated when LOCK is low.
22	ROUT[12]	output	LVCMOS receiver parallel data output, Group 2 (ROUT[15:8]); tri-stated when LOCK is low.
23	LOCK	output	Receiver PLL status: H = PLL locked; L = unlocked, with ROUT[23:0] and RCLK tri-stated.
24	RCLK	output	LVCMOS parallel interface clock output; strobe edge set by the RRFB pin.
25	VSS	power_in	Digital ground for the LVCMOS outputs.
26	VDD	power_in	Digital voltage supply for the LVCMOS outputs, 3.0V to 3.6V (3.3V nominal).
27	ROUT[11]	output	LVCMOS receiver parallel data output, Group 2 (ROUT[15:8]); tri-stated when LOCK is low.
28	ROUT[10]	output	LVCMOS receiver parallel data output, Group 2 (ROUT[15:8]); tri-stated when LOCK is low.
29	ROUT[9]	output	LVCMOS receiver parallel data output, Group 2 (ROUT[15:8]); tri-stated when LOCK is low.
30	ROUT[8]	output	LVCMOS receiver parallel data output, Group 2 (ROUT[15:8]); tri-stated when LOCK is low.
31	VSS	power_in	Digital ground for the logic.
32	VDD	power_in	Digital voltage supply for the logic, 3.0V to 3.6V (3.3V nominal).
33	RES0	unconnected	No connection, not physically connected to the die; leave open or tie LOW.
34	RES0	unconnected	No connection, not physically connected to the die; leave open or tie LOW.
35	ROUT[7]	output	LVCMOS receiver parallel data output, Group 1 (ROUT[7:0]); also carries the BIST error count when BISTM = H.
36	ROUT[6]	output	LVCMOS receiver parallel data output, Group 1 (ROUT[7:0]); also carries the BIST error count when BISTM = H.
37	ROUT[5]	output	LVCMOS receiver parallel data output, Group 1 (ROUT[7:0]); also carries the BIST error count when BISTM = H.
38	ROUT[4]	output	LVCMOS receiver parallel data output, Group 1 (ROUT[7:0]); also carries the BIST error count when BISTM = H.
39	VSS	power_in	Digital ground for the LVCMOS outputs.
40	VDD	power_in	Digital voltage supply for the LVCMOS outputs, 3.0V to 3.6V (3.3V nominal).
41	ROUT[3]	output	LVCMOS receiver parallel data output, Group 1 (ROUT[7:0]); also carries the BIST error count when BISTM = H.
42	ROUT[2]	output	LVCMOS receiver parallel data output, Group 1 (ROUT[7:0]); also carries the BIST error count when BISTM = H.
43	ROUT[1]	output	LVCMOS receiver parallel data output, Group 1 (ROUT[7:0]); also carries the BIST error count when BISTM = H.
44	ROUT[0]	output	LVCMOS receiver parallel data output, Group 1 (ROUT[7:0]); also carries the BIST error count when BISTM = H.
45	PASS	output	@Speed BIST pass flag: L = BIST failure; H = 1x10-9 error rate achieved across the link (LOCK must be H before BIST is enabled).
46	VDD	power_in	Digital voltage supply for the logic, 3.0V to 3.6V (3.3V nominal).
47	VSS	power_in	Digital ground for the logic.
48	RPWDNB	input	Receiver power down bar: H = receiver enabled; L = power-down, with ROUT[23:0], RCLK and LOCK tri-stated and the PLL shut down.
49	PTOSEL	input	Progressive Turn On selection: H = ROUT in three groups of eight, about ±1 UI to ±2 UI apart relative to RCLK; L = PTO spread mode.
50	RES0	input	Reserved; this pin must be tied LOW.
51	VDD	power_in	Analog LVDS voltage supply, 3.0V to 3.6V (3.3V nominal).
52	VSS	power_in	Analog LVDS ground.
53	RIN+	input	Receiver LVDS true (+) input; terminate with 100Ω across RIN+/RIN- and AC-couple with a 100nF capacitor.
54	RIN-	input	Receiver LVDS inverted (-) input; terminate with 100Ω across RIN+/RIN- and AC-couple with a 100nF capacitor.
55	RRFB	input	Receiver clock edge select: H = ROUT strobed on the rising RCLK edge; L = falling edge.
56	VSS	power_in	Analog ground for the PLL VCO.
57	VDD	power_in	Analog voltage supply for the PLL VCO, 3.0V to 3.6V (3.3V nominal).
58	VSS	power_in	Analog ground for the PLL.
59	VDD	power_in	Analog voltage supply for the PLL, 3.0V to 3.6V (3.3V nominal).
60	REN	input	Receiver data enable: H = ROUT[23:0] and RCLK enabled; L = they are disabled (tri-state) while the PLL stays locked.
61	BISTEN	input	BIST mode enable: L = normal mode (default); H = BIST mode active, with status on the PASS pin.
62	BISTM	input	BIST mode select: L = per-bit error status on ROUT (default); H = accumulated error count (up to 255) on ROUT[7:0].
63	RAOFF	input	Randomizer control: H = backwards compatible mode for use with the DS90C241 serializer; L = additional randomization ON (default).
64	SLEW	input	LVCMOS output slew rate control: L = low drive output at 2mA (default); H = high drive output at 4mA.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TQFP-64(10x10)
Category	Interface
Pins	64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply Voltage (VDD)	VDD	3	3.3	3.6	V		8
Operating Free Air Temperature (TA)	TA	-40	25	105	°C		8
Clock Rate		5		43	MHz		8
Supply Noise		-100		100	mVP-P		8
Supply Voltage (VDD)	VDD	-0.3		4	V		7
LVCMOS Input Voltage		-0.3			V		7
LVCMOS Output Voltage		-0.3			V		7
LVDS Receiver Input Voltage		-0.3		3.9	V		7
Junction Temperature				150	°C		7
Lead Temperature (Soldering)				260	°C	soldering, 4 seconds	7
Storage Temperature	Tstg	-65		150	°C		7
High-Level Input Voltage	VIH	2			V	Rx: RPWDNB, RRFB, REN, PTOSEL, BISTEN, BISTM, SLEW, RES0	8
Low-Level Input Voltage	VIL			0.8	V		8
Input Clamp Voltage	VCL	-1.5		-0.8	V	ICL = −18mA	8
Input Current	IIN	-10	2	10	µA	VIN = 0V or 3.6V; Rx: RRFB, REN, PTOSEL, BISTEN, BISTM, SLEW, RES0	8
Input Current (RPWDNB)	IIN	-20	5	20	µA	VIN = 0V or 3.6V; Rx: RPWDNB	8
High-Level Output Voltage	VOH	2.3	3		V	IOH = −2mA, SLEW = L; IOH = −4mA, SLEW = H; Rx: ROUT[0:23], RCLK, LOCK, PASS	8
Low-Level Output Voltage	VOL		0.33	0.5	V	IOL = 2mA, SLEW = L; IOL = 4mA, SLEW = H	8
Output Short Circuit Current	IOS	-110	-70	-40	mA	VOUT = 0V	8
Tri-state Output Current	IOZ	-30	0.4	30	µA	RPWDNB, REN = 0V, VOUT = 0V or VDD; Rx: ROUT[0:23], RCLK, LOCK, PASS	8
Differential Threshold High Voltage	VTH			50	mV	VCM = 1.8V; Rx: RIN+, RIN−	8
Differential Threshold Low Voltage	VTL	-50			mV		8
Input Current (LVDS)	IIN		100	250	µA	VIN = 2.4V, VDD = 3.6V	8
Deserializer Total Supply Current (checkerboard)	IDDR		85	105	mA	CL = 4pF, SLEW = H, f = 43MHz, checkerboard pattern, LVCMOS Output	9
Deserializer Total Supply Current (random)	IDDR		80	100	mA	CL = 4pF, SLEW = H, f = 43MHz, random pattern, LVCMOS Output	9
Deserializer Supply Current Power-down	IDDRZ			50	µA	RPWDNB = 0V (All other LVCMOS Inputs = 0V, RIN+/RIN- = 0V)	9
Receiver out Clock Period	tRCP	23.25		200	ns	tRCP = tTCP, PTOSEL = H	10
RCLK Duty Cycle	tRDC	45	50	55	%	PTOSEL = H, SLEW = L	10
LVCMOS Low-to-High Transition Time	tCLH	1.5		2.5	ns	CL = 4pF (lumped load), SLEW = H; ROUT [0:23], RCLK, LOCK	10
LVCMOS High-to-Low Transition Time	tCHL	1.5		2.5	ns	CL = 4pF (lumped load), SLEW = H; ROUT [0:23], RCLK, LOCK	10
LVCMOS Low-to-High Transition Time	tCLH	2		3.5	ns	CL = 4pF (lumped load), SLEW = L; ROUT [0:23], RCLK, LOCK	10
LVCMOS High-to-Low Transition Time	tCHL	2		3.5	ns	CL = 4pF (lumped load), SLEW = L; ROUT [0:23], RCLK, LOCK	10
HIGH to Tri-state Delay	tHZR	3		10	ns	PTOSEL = H	11
LOW to Tri-state Delay	tLZR	3		10	ns		11
Tri-state to HIGH Delay	tZHR	3		10	ns		11
Tri-state to LOW Delay	tZLR	3		10	ns		11
Receiver Input Tolerance Left	RxIN_TOL-L	0.25			UI	5MHz-43MHz; See Figure 5-17	11
Receiver Input Tolerance Right	RxIN_TOL-R	0.25			UI	5MHz-43MHz; See Figure 5-17	11
Thermal Resistance Junction-to-Ambient (4-layer, derating)	RθJA		42.8		°C/W	DS90UR124 64L TQFP, 4-layer board; derating 1/RθJA above +25°C	7
Thermal Resistance Junction-to-Ambient (2-layer, derating)	RθJA		67.2		°C/W	DS90UR124 64L TQFP, 2-layer board; derating 1/RθJA above +25°C	7
Thermal Resistance Junction-to-Case (derating)	RθJC		14.6		°C/W	DS90UR124 64L TQFP	7
Thermal Resistance Junction-to-Ambient	RθJA		58.1		°C/W	PAG [TQFP] 64 pins	8
Thermal Resistance Junction-to-Case (top)	RθJC(top)		13		°C/W	PAG [TQFP] 64 pins	8
Thermal Resistance Junction-to-Board	RθJB		30.4		°C/W	PAG [TQFP] 64 pins	8

CAD (KiCad official)

Symbol: DS90UR124QVSX
Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
3D model files: ds90ur124qvsx-etched.step / ds90ur124qvsx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds90ur124qvsx.step / ds90ur124qvsx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (45 pp, sha256 fbb642ca8b1cda5a, retrieved 2026-11-11, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

DS90UR124QVSX

Verified DS90UR124QVSX

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

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Datasheet

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