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DS90UB914ATRHSJQ1

Texas Instruments · Serializers / Deserializers · WQFN-48-EP(7x7)

DS90UB914ATRHSJQ1 from Texas Instruments, in a WQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SDA	bidirectional	Open-drain data line of the I2C-compatible bidirectional control bus, requiring an external pullup resistor to VDDIO.
2	SCL	bidirectional	Open-drain clock line of the I2C-compatible bidirectional control bus, requiring an external pullup resistor to VDDIO.
3	VDDSSCG	power_in	SSCG PLL analog power supply, 1.8 V ±5%.
4	OSS_SEL	input	Output Sleep State Select LVCMOS input with internal pulldown, used with OEN to set output states (Table 3).
5	OEN	input	Output Enable LVCMOS input with internal pulldown, used with OSS_SEL to set output states (Table 3).
6	BISTEN	input	BIST enable LVCMOS input with internal pulldown; high enables BIST mode, low disables it.
7	VDDIO3	power_in	LVCMOS I/O buffer power for outputs and control inputs, 1.8 V ±5% or 3.3 V ±10%.
8	PCLK	output	LVCMOS pixel clock output with strobe edge set by the RRFB register; active before LOCK in 12-bit low-frequency and 10-bit modes, and at the same time as LOCK in 12-bit high-frequency mode.
9	VSYNC	output	LVCMOS vertical sync output, restricted to one transition per 10 PCLK cycles in 10-bit mode; leave open if unused.
10	HSYNC	output	LVCMOS horizontal sync output, restricted to one transition per 10 PCLK cycles in 10-bit mode; leave open if unused.
11	ROUT11	output	LVCMOS parallel data output bit 11, active only in 12-bit modes; leave unconnected in 10-bit mode or if unused.
12	ROUT10	output	LVCMOS parallel data output bit 10, active only in 12-bit modes; leave unconnected in 10-bit mode or if unused.
13	ROUT9	output	LVCMOS parallel data output bit 9, active in 10-bit and 12-bit modes; leave unconnected if unused.
14	ROUT8	output	LVCMOS parallel data output bit 8, active in 10-bit and 12-bit modes; leave unconnected if unused.
15	ROUT7	output	LVCMOS parallel data output bit 7, active in 10-bit and 12-bit modes; leave unconnected if unused.
16	ROUT6	output	LVCMOS parallel data output bit 6, active in 10-bit and 12-bit modes; leave unconnected if unused.
17	VDDD	power_in	Digital core power supply, 1.8 V ±5%.
18	ROUT5	output	LVCMOS parallel data output bit 5, active in 10-bit and 12-bit modes; leave unconnected if unused.
19	ROUT4	output	LVCMOS parallel data output bit 4, active in 10-bit and 12-bit modes; leave unconnected if unused.
20	VDDIO2	power_in	LVCMOS I/O buffer power for outputs and control inputs, 1.8 V ±5% or 3.3 V ±10%.
21	ROUT3	output	LVCMOS parallel data output bit 3, active in 10-bit and 12-bit modes; leave unconnected if unused.
22	ROUT2	output	LVCMOS parallel data output bit 2, active in 10-bit and 12-bit modes; leave unconnected if unused.
23	ROUT1	output	LVCMOS parallel data output bit 1, active in 10-bit and 12-bit modes; leave unconnected if unused.
24	ROUT0	output	LVCMOS parallel data output bit 0, active in 10-bit and 12-bit modes; leave unconnected if unused.
25	GPIO3	bidirectional	LVCMOS general-purpose I/O that can be an input for serializer GPO3 or an output following local register settings (output only with external oscillator); leave open if unused.
26	GPIO2	bidirectional	LVCMOS general-purpose I/O that can be an input for serializer GPO2 or an output following local register settings (output only with external oscillator); leave open if unused.
27	GPIO1	bidirectional	LVCMOS general-purpose I/O that can be an input for serializer GPO1 or an output following local register settings, also selects the BIST clock source; leave open if unused.
28	GPIO0	bidirectional	LVCMOS general-purpose I/O that can be an input for serializer GPO0 or an output following local register settings, also selects the BIST clock source; leave open if unused.
29	VDDIO1	power_in	LVCMOS I/O buffer power for outputs and control inputs, 1.8 V ±5% or 3.3 V ±10%.
30	PDB	input	Power-down LVCMOS input with internal pulldown; high enables the deserializer, low powers it down and resets control registers to defaults.
31	VDDCML1	power_in	CML and bidirectional control channel drive power supply, 1.8 V ±5%.
32	RIN1+	bidirectional	Noninverting CML FPD-Link III input and bidirectional control channel, AC-coupled with a 0.1 µF capacitor; leave open if unused.
33	RIN1-	bidirectional	Inverting CML FPD-Link III input and bidirectional control channel, AC-coupled with 0.1 µF (0.047 µF in series with 50 Ω to GND for single-ended coax); leave open if unused.
34	IDx[1]	input	Analog device ID address select (IDx[1]) setting the I2C slave address, with resistor to ground and 10 kΩ pullup to the 1.8 V rail.
35	IDx[0]	input	Analog device ID address select (IDx[0]) setting the I2C slave address, with resistor to ground and 10 kΩ pullup to the 1.8 V rail.
36	VDDR	power_in	Rx analog power supply, 1.8 V ±5%.
37	MODE	input	Analog mode select input selecting 12-bit low-frequency (25-50 MHz), 12-bit high-frequency (37.5-75 MHz) or 10-bit (50-100 MHz) operation via a resistor to ground and 10 kΩ pullup to 1.8 V.
38	CMLOUTP	output	CML loop-through output; route to test point or leave open if unused.
39	CMLOUTN	output	CML loop-through output; route to test point or leave open if unused.
40	VDDCML0	power_in	CML and bidirectional control channel drive power supply, 1.8 V ±5%.
41	RIN0+	bidirectional	Noninverting CML FPD-Link III input and bidirectional control channel, AC-coupled with a 0.1 µF capacitor; leave open if unused.
42	RIN0-	bidirectional	Inverting CML FPD-Link III input and bidirectional control channel, AC-coupled with 0.1 µF (0.047 µF in series with 50 Ω to GND for single-ended coax); leave open if unused.
43	RES	input	Reserved pin that must always be tied low.
44	RES	input	Reserved pin that must always be tied low.
45	VDDPLL	power_in	PLL analog power supply, 1.8 V ±5%.
46	SEL	input	MUX select input with internal pulldown; low selects RIN0+/- and high selects RIN1+/- as the active channel.
47	PASS	output	BIST pass output, high for error-free transmission and low when payload errors are detected; leave open if unused.
48	LOCK	output	LOCK status output; high indicates the PLL is locked and outputs are active, low indicates unlocked with output states set by OSS_SEL.
49	VSS	power_in	Exposed die attach pad that must be grounded, connected to the ground plane with at least 16 vias.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	WQFN-48-EP(7x7)
Category	Communication Interface Chip/UART/485/232
Pins	49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage VDD_n (1.8 V)		-0.3		2.5	V		9
Supply voltage VDDIO		-0.3		4	V		9
Junction temperature				150	°C		9
Storage temperature	Tstg	-65		150	°C		9
Supply Voltage VDD_n	VDD_n	1.71	1.8	1.89	V		9
LVCMOS Supply Voltage (VDDIO = 1.8 V)	VDDIO	1.71	1.8	1.89	V	VDDIO = 1.8 V	9
LVCMOS Supply Voltage (VDDIO = 3.3 V)	VDDIO	3	3.3	3.6	V	VDDIO = 3.3 V	9
Supply noise VDD_n (1.8 V)				25	mVp-p		9
Supply noise VDDIO (1.8 V)				25	mVp-p		9
Supply noise VDDIO (3.3 V)				50	mVp-p		9
Power-Over-Coax supply noise				10	mVp-p	f = 30 Hz - 1 KHz, trise > 100 µs; measured differentially between DOUT+ and DOUT- (coax mode only)	9
Operating Free Air Temperature	TA	-40	25	105	°C		9
PCLK Clock Frequency		25		100	MHz		9
Junction-to-ambient thermal resistance	RθJA		29.7		°C/W	RHS (WQFN) 48 pins	10
Junction-to-case (top) thermal resistance	RθJC(top)		10.9		°C/W	RHS (WQFN) 48 pins	10
Junction-to-board thermal resistance	RθJB		6.7		°C/W	RHS (WQFN) 48 pins	10
Junction-to-case (bottom) thermal resistance	RθJC(bot)		2.3		°C/W	RHS (WQFN) 48 pins	10
High Level Input Voltage (3.3 V I/O)	VIH	2			V	VIN = 3 V to 3.6 V	10
Low Level Input Voltage (3.3 V I/O)	VIL			0.8	V	VIN = 3 V to 3.6 V	10
Input Current (3.3 V I/O)	IIN	-20	1	20	µA	VIN = 0 V or 3.6 V, VIN = 3 V to 3.6 V	10
High Level Output Voltage (3.3 V I/O)	VOH	2.4			V	VDDIO = 3 V to 3.6 V, IOH = −4 mA	10
Low Level Output Voltage (3.3 V I/O)	VOL			0.4	V	VDDIO = 3 V to 3.6 V, IOL = 4 mA	10
TRI-STATE Output Current (3.3 V I/O)	IOZ	-20		20	µA	PDB = 0 V, VOUT = 0 V or VDD, LVCMOS Outputs, GPO Outputs	10
Input Current (1.8 V I/O)	IIN	-20	1	20	µA	VIN = 0 V or 1.89 V, VIN = 1.71 V to 1.89 V	10
Low Level Output Voltage (1.8 V I/O)	VOL			0.45	V	VDDIO = 1.71 V to 1.89 V IOL = 4 mA	10
TRI-STATE Output Current (1.8 V I/O)	IOZ	-20		20	µA	PDB = 0 V, VOUT = 0 V or VDD, LVCMOS Outputs, GPO Outputs	10
CML receiver input current	IIN	-20	1	20	µA	VIN = VDD or 0 V, VDD = 1.89 V	11
Differential Internal Termination Resistance	RT	80	100	120	Ω	Differential across RIN+ and RIN-	11
Single-ended Termination Resistance	RT	40	50	60	Ω	RIN+ or RIN-	11
Differential Input Voltage	VID	210			mV	Back Channel Disabled, (Figure 4)	11
Single-Ended Input Voltage	VIN	105			mV	Back Channel Disabled, (Figure 4)	11
Back Channel Frequency	ƒBC	3.3		4.2	MHz		11
Back Channel Differential Output Voltage	VOD-BC	350		540	mV		11
Back Channel Single-Ended Output Voltage	VOUT-BC	182		270	mV		11
CML monitor Differential Output Eye Opening	Ew	0.45			UI	RL = 100 Ω, Jitter Frequency > f/15 (Figure 9)	11
CML monitor Differential Output Eye Height	EH	200			mV	RL = 100 Ω, Jitter Frequency > f/15 (Figure 9)	11
Deserializer VDDIO supply current	IDDIOR		22	42	mA	VDDIO=1.89 V, CL=8 pF, Worst Case Pattern, f = 100 MHz, 10-bit mode	12
Deserializer VDDIO supply current	IDDIOR		42	55	mA	VDDIO=3.6 V, CL=8 pF, Worst Case Pattern, f = 100 MHz, 10-bit mode	12
Deserializer VDDIO supply current	IDDIOR		25	38	mA	VDDIO=3.6 V, CL=8 pF, Worst Case Pattern, f = 50 MHz, 12-bit low freq mode	12
Deserializer VDD_n supply current	IDDR		64	110	mA	VDD_n = 1.89 V, CL= 4 pF, Worst Case Pattern, f = 100 MHz, 10-bit mode	13
Deserializer VDD_n supply current	IDDR		67	114	mA	VDD_n = 1.89 V, CL= 4 pF, Worst Case Pattern, f = 75 MHz, 12-bit high freq mode	13
Deserializer VDD_n supply current	IDDR		63	96	mA	VDD_n = 1.89 V, CL= 4 pF, Worst Case Pattern, f = 50 MHz, 12-bit low freq mode	13
Deserializer supply current power down	IDDRZ		42	900	µA	PDB = 0 V, All other LVCMOS Inputs = 0 V, VDDIO = 1.89 V, Default Registers	13
Deserializer VDDIO supply current power down	IDDIORZ		8	40	µA	PDB = 0 V, All other LVCMOS Inputs = 0 V, VDDIO = 1.89 V	13
Deserializer VDDIO supply current power down	IDDIORZ		360	800	µA	PDB = 0 V, All other LVCMOS Inputs = 0 V, VDDIO = 3.6 V	13
SCL Clock Frequency, Fast Mode	fSCL			400	kHz	Fast Mode	14
SCL Clock Frequency, Standard Mode	fSCL			100	kHz	Standard Mode	14
SCL Low Period, Fast Mode	tLOW	1.3			µs	Fast Mode	14
SCL High Period, Fast Mode	tHIGH	0.6			µs	Fast Mode	14
SCL & SDA Rise Time, Fast Mode	tr			300	ns	Fast Mode	14
Output Low Level SDA	VOL	0		0.36	V	SDA, VDDIO = 1.8 V, IOL= 0.9 mA	15
Output Low Level SDA	VOL	0		0.4	V	SDA, VDDIO = 3.3 V, IOL= 1.6 mA	15
I2C Input Current	IIN	-10		10	µA	SDA or SCL, VIN= VDDIO OR GND	15
Receiver Output Clock Period, 10-bit mode	tRCP	10		20	ns	10-bit mode 50 MHz, 100 MHz PCLK (Figure 8)	15
PCLK Duty Cycle, 10-bit mode	tPDC	45	50	55	%	10-bit mode 50 MHz, 100 MHz PCLK	15
LVCMOS Low-to-High Transition Time (PCLK)	tCLH	1.3	2	2.8	ns	VDDIO: 1.71 V to 1.89 V or 3 V to 3.6 V, CL = 8 pF (lumped load), Default Registers (Figure 6)	15
LVCMOS Low-to-High Transition Time (ROUT, HS, VS)	tDLH	1	2.5	4	ns	VDDIO: 1.71 V to 1.89 V or 3 V to 3.6 V, CL = 8 pF (lumped load), Default Registers (Figure 6)	15
Deserializer Data Lock Time	tDDLT		15	22	ms	With Adaptive Equalization (Figure 5), 10-bit mode 50 - 100 MHz	16
Receiver Clock Jitter, 10-bit mode	tRCJ		20	30	ps	SSCG[3:0] = OFF, PCLK = 100 MHz	16

CAD (KiCad official)

Symbol: DS90UB914ATRHSJQ1
Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
3D model: WQFN-48-EP(7x7) (KiCad packages3D, STEP)
3D model files: ds90ub914atrhsjq1-etched.step / ds90ub914atrhsjq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds90ub914atrhsjq1.step / ds90ub914atrhsjq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (69 pp, sha256 d4b97b56a1a2bbaf, retrieved 2026-10-23, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF