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DS90UB913ATRTVRQ1

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Texas Instruments Serializers, Deserializers, WQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DS90UB913ATRTVRQ1

Texas Instruments · Serializers, Deserializers · WQFN-32-EP(5x5)

DS90UB913ATRTVRQ1 from Texas Instruments, in a WQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 HSYNC input Horizontal SYNC LVCMOS input with pulldown; in 10-bit mode restricted to no more than one transition per 10 PCLK cycles, leave open if unused.
2 VSYNC input Vertical SYNC LVCMOS input with pulldown; in 10-bit mode restricted to no more than one transition per 10 PCLK cycles, leave open if unused.
3 PCLK input Pixel clock LVCMOS input with pulldown; strobe edge set by TRFB control register 0x03[0].
4 SCL bidirectional Open-drain clock line of the I2C-compatible bidirectional control bus, requires an external pullup resistor to VDDIO.
5 SDA bidirectional Open-drain data line of the I2C-compatible bidirectional control bus, requires an external pullup resistor to VDDIO.
6 ID[x] input Analog device I2C address select, set with a resistor (RID) to ground and a 10-kΩ pullup to the 1.8 V rail.
7 RES input Reserved LVCMOS input with pulldown that must be tied LOW.
8 MODE input Analog device mode select between imager PCLK and external oscillator operation, set with a resistor (Rmode) to ground and a 10-kΩ pullup to 1.8 V.
9 PDB input Power-down input with pulldown: H enables the serializer, L powers it down, shutting down the PLL and resetting registers to defaults.
10 VDDPLL power_in Analog PLL power supply, 1.8 V ±5%.
11 VDDT power_in Analog Tx power supply, 1.8 V ±5%.
12 DOUT- bidirectional Inverting CML differential output and bidirectional control channel input, AC coupled with 0.1 µF (0.047 µF in series with 50 Ω to GND for single-ended coax).
13 DOUT+ bidirectional Non-inverting CML differential output and bidirectional control channel input, must be AC coupled with a 0.1-µF capacitor.
14 VDDCML power_in CML and bidirectional channel driver power supply, 1.8 V ±5%.
15 GPO[0] output LVCMOS general-purpose output driven from deserializer GPIO0 or a local register, leave open if unused.
16 GPO[1] output LVCMOS general-purpose output driven from deserializer GPIO1 or a local register, leave open if unused.
17 GPO[2]/CLKOUT output LVCMOS general-purpose output or external-oscillator-mode clock output; pull to GND with a minimum 40-kΩ resistor to ensure LOW when PDB goes HIGH.
18 GPO[3]/CLKIN bidirectional LVCMOS general-purpose output or external oscillator clock input, leave open if unused.
19 DIN[0] input Parallel data input bit 0, LVCMOS with pulldown; unused inputs should be No Connect.
20 DIN[1] input Parallel data input bit 1, LVCMOS with pulldown; unused inputs should be No Connect.
21 DIN[2] input Parallel data input bit 2, LVCMOS with pulldown; unused inputs should be No Connect.
22 DIN[3] input Parallel data input bit 3, LVCMOS with pulldown; unused inputs should be No Connect.
23 DIN[4] input Parallel data input bit 4, LVCMOS with pulldown; unused inputs should be No Connect.
24 DIN[5] input Parallel data input bit 5, LVCMOS with pulldown; unused inputs should be No Connect.
25 VDDIO power_in I/O stage power for single-ended inputs and SDA/SCL, connectable to 1.8 V ±5%, 2.8 V ±10% or 3.3 V ±10%.
26 DIN[6] input Parallel data input bit 6, LVCMOS with pulldown; unused inputs should be No Connect.
27 DIN[7] input Parallel data input bit 7, LVCMOS with pulldown; unused inputs should be No Connect.
28 VDDD power_in Digital power supply, 1.8 V ±5%.
29 DIN[8] input Parallel data input bit 8, LVCMOS with pulldown; unused inputs should be No Connect.
30 DIN[9] input Parallel data input bit 9, LVCMOS with pulldown; active in 10-bit and 12-bit modes, unused inputs should be No Connect.
31 DIN[10] input Parallel data input bit 10, LVCMOS with pulldown; active only in 12-bit mode, inactive and No Connect in 10-bit mode.
32 DIN[11] input Parallel data input bit 11, LVCMOS with pulldown; active only in 12-bit mode, inactive and No Connect in 10-bit mode.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-32-EP(5x5)
Category Interface
Pins 33

CAD (KiCad official)

  • Symbol: DS90UB913ATRTVRQ1
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: WQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: ds90ub913atrtvrq1-etched.step / ds90ub913atrtvrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds90ub913atrtvrq1.step / ds90ub913atrtvrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (57 pp, sha256 ace8cb05a1a45ee1, retrieved 2026-10-05, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF