DS90UB904QSQX

{
  "slug": "ds90ub904qsqx",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Serializers / Deserializers, WQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "interface ics",
    "ds90ub904qsqx",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
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    "path": "docs/hero.png"
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    "README.md",
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    "ds90ub904qsqx.kicad_mod",
    "ds90ub904qsqx.glb",
    "ds90ub904qsqx.step",
    "ds90ub904qsqx.lbr",
    "docs/hero.png",
    "docs/ds90ub904qsqx-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
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    "ds90ub904qsqx-hero.overlay.json",
    "ds90ub904qsqx-etched.glb"
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  "component": {
    "mpn": "DS90UB904QSQX",
    "manufacturer": "Texas Instruments",
    "package": "WQFN-48-EP(7x7)",
    "pin_count": 49,
    "category": "Interface ICs",
    "subcategory": "Serializers / Deserializers",
    "datasheet": "https://www.ti.com/lit/ds/symlink/ds90ub904qsqx.pdf",
    "parts": {
      "symbol": "ds90ub904qsqx.kicad_sym",
      "footprint": "ds90ub904qsqx.kicad_mod",
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      "model_3d_step": "ds90ub904qsqx-etched.step",
      "model_3d_step_plain": "ds90ub904qsqx.step",
      "lbr": "ds90ub904qsqx.lbr"
    },
    "distributor_links": {
      "lcsc": "C2672675"
    },
    "distributor_check": {
      "checked_at": "2026-11-02T19:16:50Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "no match"
      },
      "mouser": {
        "pn": null,
        "status": "no match"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "SDA",
        "type": "bidirectional",
        "description": "Open-drain data line of the I2C-compatible bidirectional control bus, requiring an external pull-up resistor to VDDIO."
      },
      {
        "number": "2",
        "name": "SCL",
        "type": "bidirectional",
        "description": "Open-drain clock line of the I2C-compatible bidirectional control bus, requiring an external pull-up resistor to VDDIO."
      },
      {
        "number": "3",
        "name": "VDDSSCG",
        "type": "power_in",
        "description": "SSCG digital power, 1.8V ±5%, which must be connected whether or not the SSCG function is in operation."
      },
      {
        "number": "4",
        "name": "PCLK",
        "type": "output",
        "description": "LVCMOS pixel clock output whose strobe edge is set by the RRFB control register."
      },
      {
        "number": "5",
        "name": "ROUT[20]",
        "type": "output",
        "description": "LVCMOS parallel data output bit 20."
      },
      {
        "number": "6",
        "name": "ROUT[19]",
        "type": "output",
        "description": "LVCMOS parallel data output bit 19."
      },
      {
        "number": "7",
        "name": "VDDIO3",
        "type": "power_in",
        "description": "LVCMOS I/O buffer power for the single-ended outputs and control inputs, 1.8V ±5% or 3.3V ±10%."
      },
      {
        "number": "8",
        "name": "ROUT[18]",
        "type": "output",
        "description": "LVCMOS parallel data output bit 18."
      },
      {
        "number": "9",
        "name": "ROUT[17]",
        "type": "output",
        "description": "LVCMOS parallel data output bit 17."
      },
      {
        "number": "10",
        "name": "ROUT[16]",
        "type": "output",
        "description": "LVCMOS parallel data output bit 16."
      },
      {
        "number": "11",
        "name": "ROUT[15]",
        "type": "output",
        "description": "LVCMOS parallel data output bit 15."
      },
      {
        "number": "12",
        "name": "ROUT[14]",
        "type": "output",
        "description": "LVCMOS parallel data output bit 14."
      },
      {
        "number": "13",
        "name": "ROUT[13]",
        "type": "output",
        "description": "LVCMOS parallel data output bit 13."
      },
      {
        "number": "14",
        "name": "ROUT[12]",
        "type": "output",
        "description": "LVCMOS parallel data output bit 12."
      },
      {
        "number": "15",
        "name": "ROUT[11]",
        "type": "output",
        "description": "LVCMOS parallel data output bit 11."
      },
      {
        "number": "16",
        "name": "ROUT[10]",
        "type": "output",
        "description": "LVCMOS parallel data output bit 10."
      },
      {
        "number": "17",
        "name": "VDDD",
        "type": "power_in",
        "description": "Digital core power, 1.8V ±5%."
      },
      {
        "number": "18",
        "name": "ROUT[9]",
        "type": "output",
        "description": "LVCMOS parallel data output bit 9."
      },
      {
        "number": "19",
        "name": "ROUT[8]",
        "type": "output",
        "description": "LVCMOS parallel data output bit 8."
      },
      {
        "number": "20",
        "name": "VDDIO2",
        "type": "power_in",
        "description": "LVCMOS I/O buffer power for the single-ended outputs and control inputs, 1.8V ±5% or 3.3V ±10%."
      },
      {
        "number": "21",
        "name": "ROUT[7]",
        "type": "output",
        "description": "LVCMOS parallel data output bit 7."
      },
      {
        "number": "22",
        "name": "ROUT[6]",
        "type": "output",
        "description": "LVCMOS parallel data output bit 6."
      },
      {
        "number": "23",
        "name": "ROUT[5]",
        "type": "output",
        "description": "LVCMOS parallel data output bit 5."
      },
      {
        "number": "24",
        "name": "ROUT[4]",
        "type": "output",
        "description": "LVCMOS parallel data output bit 4."
      },
      {
        "number": "25",
        "name": "ROUT[3]",
        "type": "output",
        "description": "LVCMOS parallel data output bit 3."
      },
      {
        "number": "26",
        "name": "ROUT[2]",
        "type": "output",
        "description": "LVCMOS parallel data output bit 2."
      },
      {
        "number": "27",
        "name": "ROUT[1]",
        "type": "output",
        "description": "LVCMOS parallel data output bit 1."
      },
      {
        "number": "28",
        "name": "ROUT[0]",
        "type": "output",
        "description": "LVCMOS parallel data output bit 0."
      },
      {
        "number": "29",
        "name": "VDDIO1",
        "type": "power_in",
        "description": "LVCMOS I/O buffer power for the single-ended outputs and control inputs, 1.8V ±5% or 3.3V ±10%."
      },
      {
        "number": "30",
        "name": "GPI[3]",
        "type": "input",
        "description": "LVCMOS general-purpose input that can be used to control and respond to various commands."
      },
      {
        "number": "31",
        "name": "GPI[2]",
        "type": "input",
        "description": "LVCMOS general-purpose input that can be used to control and respond to various commands."
      },
      {
        "number": "32",
        "name": "GPI[1]",
        "type": "input",
        "description": "LVCMOS general-purpose input that can be used to control and respond to various commands."
      },
      {
        "number": "33",
        "name": "GPI[0]",
        "type": "input",
        "description": "LVCMOS general-purpose input that can be used to control and respond to various commands."
      },
      {
        "number": "34",
        "name": "LOCK",
        "type": "output",
        "description": "LOCK status output: high when the PLL is locked, low when unlocked (ROUT and PCLK states then set by the OSS_SEL control register); may be used as link status."
      },
      {
        "number": "35",
        "name": "PDB",
        "type": "input",
        "description": "Power-down input with pull-down: high enables the deserializer, low powers it down and resets control register data to default values."
      },
      {
        "number": "36",
        "name": "VDDR",
        "type": "power_in",
        "description": "Rx analog power, 1.8V ±5%."
      },
      {
        "number": "37",
        "name": "PASS",
        "type": "output",
        "description": "BIST pass output: high for error-free transmission, low if one or more errors were detected in the received payload; leave open if unused, test point recommended."
      },
      {
        "number": "38",
        "name": "RES/CMLOUTP",
        "type": "output",
        "description": "Reserved pin / non-inverting CML monitor output of the equalized differential signal, enabled via control registers; route to a test point or leave open if unused."
      },
      {
        "number": "39",
        "name": "RES/CMLOUTN",
        "type": "output",
        "description": "Reserved pin / inverting CML monitor output of the equalized differential signal, enabled via control registers; route to a test point or leave open if unused."
      },
      {
        "number": "40",
        "name": "VDDCML",
        "type": "power_in",
        "description": "Bidirectional channel driver analog power, 1.8V ±5%."
      },
      {
        "number": "41",
        "name": "RIN+",
        "type": "bidirectional",
        "description": "Non-inverting CML differential input and bidirectional control channel output; the interconnect must be AC coupled with a 100 nF capacitor."
      },
      {
        "number": "42",
        "name": "RIN-",
        "type": "bidirectional",
        "description": "Inverting CML differential input and bidirectional control channel output; the interconnect must be AC coupled with a 100 nF capacitor."
      },
      {
        "number": "43",
        "name": "RES",
        "type": "unconnected",
        "description": "Reserved pin; leave open."
      },
      {
        "number": "44",
        "name": "BISTEN",
        "type": "input",
        "description": "BIST enable input with pull-down: high enables BIST mode, low disables it."
      },
      {
        "number": "45",
        "name": "VDDPLL",
        "type": "power_in",
        "description": "PLL analog power, 1.8V ±5%."
      },
      {
        "number": "46",
        "name": "RES",
        "type": "input",
        "description": "Reserved pin that must be tied LOW."
      },
      {
        "number": "47",
        "name": "MODE",
        "type": "input",
        "description": "I2C mode select input with pull-up: low is master mode, high is slave mode (default)."
      },
      {
        "number": "48",
        "name": "ID[x]",
        "type": "input",
        "description": "Analog device ID address select, set by a resistor to ground and a 10 kΩ pull-up to the 1.8V rail."
      },
      {
        "number": "49",
        "name": "EP",
        "type": "passive",
        "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-sonnet-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-opus-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: ROUT[20:0] and GPI[3:0] pin numbers are listed in a single table row in descending bit order; the pe; Pins 38/39 are listed as both Reserved and CMLOUTP/CMLOUTN; typed as output per the CML monitor desc; RIN+/RIN- are described as input/output CML (differential input plus bidirectional control channel o",
          "exposed pad 49 added from the footprint",
          "dropped thermal pad ['EP'] absent from footprint"
        ],
        "pages_sent": 15,
        "cost_usd": 0.3156,
        "at": "2026-11-02T19:16:17"
      },
      "datasheet": {
        "url": "https://www.ti.com/lit/ds/symlink/ds90ub904qsqx.pdf",
        "pages": 46,
        "sha256": "05583a291c80f2ba",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 49,
        "described": 49,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
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      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
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        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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          7.0,
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        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "f2b38b0b4bf967c77e683e8d4599608b9f0503055ec535b93c4ebb5d0163e916",
        "checked": "2026-11-02",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "ds90ub904qsqx-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
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        "sha256": "3d8bd64ef5f0e0c4f3b41cb72526145624a5f5e32a0e8d0d96df43c398b3a8ed",
        "checked": "2026-11-02",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}