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Texas Instruments Serializers / Deserializers, WQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DS90UB904QSQX

Texas Instruments · Serializers / Deserializers · WQFN-48-EP(7x7)

DS90UB904QSQX from Texas Instruments, in a WQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SDA	bidirectional	Open-drain data line of the I2C-compatible bidirectional control bus, requiring an external pull-up resistor to VDDIO.
2	SCL	bidirectional	Open-drain clock line of the I2C-compatible bidirectional control bus, requiring an external pull-up resistor to VDDIO.
3	VDDSSCG	power_in	SSCG digital power, 1.8V ±5%, which must be connected whether or not the SSCG function is in operation.
4	PCLK	output	LVCMOS pixel clock output whose strobe edge is set by the RRFB control register.
5	ROUT[20]	output	LVCMOS parallel data output bit 20.
6	ROUT[19]	output	LVCMOS parallel data output bit 19.
7	VDDIO3	power_in	LVCMOS I/O buffer power for the single-ended outputs and control inputs, 1.8V ±5% or 3.3V ±10%.
8	ROUT[18]	output	LVCMOS parallel data output bit 18.
9	ROUT[17]	output	LVCMOS parallel data output bit 17.
10	ROUT[16]	output	LVCMOS parallel data output bit 16.
11	ROUT[15]	output	LVCMOS parallel data output bit 15.
12	ROUT[14]	output	LVCMOS parallel data output bit 14.
13	ROUT[13]	output	LVCMOS parallel data output bit 13.
14	ROUT[12]	output	LVCMOS parallel data output bit 12.
15	ROUT[11]	output	LVCMOS parallel data output bit 11.
16	ROUT[10]	output	LVCMOS parallel data output bit 10.
17	VDDD	power_in	Digital core power, 1.8V ±5%.
18	ROUT[9]	output	LVCMOS parallel data output bit 9.
19	ROUT[8]	output	LVCMOS parallel data output bit 8.
20	VDDIO2	power_in	LVCMOS I/O buffer power for the single-ended outputs and control inputs, 1.8V ±5% or 3.3V ±10%.
21	ROUT[7]	output	LVCMOS parallel data output bit 7.
22	ROUT[6]	output	LVCMOS parallel data output bit 6.
23	ROUT[5]	output	LVCMOS parallel data output bit 5.
24	ROUT[4]	output	LVCMOS parallel data output bit 4.
25	ROUT[3]	output	LVCMOS parallel data output bit 3.
26	ROUT[2]	output	LVCMOS parallel data output bit 2.
27	ROUT[1]	output	LVCMOS parallel data output bit 1.
28	ROUT[0]	output	LVCMOS parallel data output bit 0.
29	VDDIO1	power_in	LVCMOS I/O buffer power for the single-ended outputs and control inputs, 1.8V ±5% or 3.3V ±10%.
30	GPI[3]	input	LVCMOS general-purpose input that can be used to control and respond to various commands.
31	GPI[2]	input	LVCMOS general-purpose input that can be used to control and respond to various commands.
32	GPI[1]	input	LVCMOS general-purpose input that can be used to control and respond to various commands.
33	GPI[0]	input	LVCMOS general-purpose input that can be used to control and respond to various commands.
34	LOCK	output	LOCK status output: high when the PLL is locked, low when unlocked (ROUT and PCLK states then set by the OSS_SEL control register); may be used as link status.
35	PDB	input	Power-down input with pull-down: high enables the deserializer, low powers it down and resets control register data to default values.
36	VDDR	power_in	Rx analog power, 1.8V ±5%.
37	PASS	output	BIST pass output: high for error-free transmission, low if one or more errors were detected in the received payload; leave open if unused, test point recommended.
38	RES/CMLOUTP	output	Reserved pin / non-inverting CML monitor output of the equalized differential signal, enabled via control registers; route to a test point or leave open if unused.
39	RES/CMLOUTN	output	Reserved pin / inverting CML monitor output of the equalized differential signal, enabled via control registers; route to a test point or leave open if unused.
40	VDDCML	power_in	Bidirectional channel driver analog power, 1.8V ±5%.
41	RIN+	bidirectional	Non-inverting CML differential input and bidirectional control channel output; the interconnect must be AC coupled with a 100 nF capacitor.
42	RIN-	bidirectional	Inverting CML differential input and bidirectional control channel output; the interconnect must be AC coupled with a 100 nF capacitor.
43	RES	unconnected	Reserved pin; leave open.
44	BISTEN	input	BIST enable input with pull-down: high enables BIST mode, low disables it.
45	VDDPLL	power_in	PLL analog power, 1.8V ±5%.
46	RES	input	Reserved pin that must be tied LOW.
47	MODE	input	I2C mode select input with pull-up: low is master mode, high is slave mode (default).
48	ID[x]	input	Analog device ID address select, set by a resistor to ground and a 10 kΩ pull-up to the 1.8V rail.
49	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	WQFN-48-EP(7x7)
Category	Interface ICs
Pins	49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply Voltage VDDn	VDDn	1.71	1.8	1.89	V		7
LVCMOS Supply Voltage VDDIO (1.8V)	VDDIO	1.71	1.8	1.89	V		7
LVCMOS Supply Voltage VDDIO (3.3V)	VDDIO	3	3.3	3.6	V		7
Operating Free Air Temperature	TA	-40	25	105	°C		7
PCLK Clock Frequency		10		43	MHz		7
Supply Noise VDDn (1.8V)				25	mVp-p		7
Supply Noise VDDIO (3.3V)				50	mVp-p		7
Supply Voltage VDDn (1.8V)	VDDn	-0.3		2.5	V		7
Supply Voltage VDDIO	VDDIO	-0.3		4	V		7
LVCMOS Input Voltage		-0.3			V	max = VDDIO + 0.3V	7
CML Receiver I/O Voltage		-0.3			V	max = VDD + 0.3V	7
Junction Temperature				150	°C		7
Storage Temperature		-65		150	°C		7
Thermal resistance junction-ambient, 48 Lead WQFN	θJA		26.9		°C/W	based on 16 thermal vias	7
Thermal resistance junction-case, 48 Lead WQFN	θJC		4.4		°C/W	based on 16 thermal vias	7
ESD HBM				8	kV	≥±8 kV	7
ESD CDM				1	kV	≥±1 kV	7
High Level Input Voltage 3.3V I/O	VIH	2			V	VIN = 3.0V to 3.6V	8
Low Level Input Voltage 3.3V I/O	VIL			0.8	V	VIN = 3.0V to 3.6V	8
Input Current 3.3V I/O	IIN	-20	1	20	µA	VIN = 0V or 3.6V, VIN = 3.0V to 3.6V	8
High Level Output Voltage 3.3V I/O	VOH	2.4			V	VDDIO = 3.0V to 3.6V, IOH = −4 mA	8
Low Level Output Voltage 3.3V I/O	VOL			0.4	V	VDDIO = 3.0V to 3.6V, IOL = +4 mA	8
Input Current 1.8V I/O	IIN	-20	1	20	µA	VIN = 0V or 1.89V, VIN = 1.71V to 1.89V	8
Low Level Output Voltage 1.8V I/O	VOL			0.45	V	VDDIO = 1.71V to 1.89V, IOL = +4 mA	8
TRI-STATE Output Current	IOZ	-20	1	20	µA	PDB = 0V, VOUT = 0V or VDD	8
Differential Threshold High Voltage	VTH			90	mV	Figure 10	9
Differential Threshold Low Voltage	VTL	-90			mV	Figure 10	9
Receiver Differential Internal Termination Resistance	RT	80	100	120	Ω	Differential across RIN+ and RIN-	9
CML Receiver Input Current	IIN	-20	1	20	µA	VIN = VDD or 0V, VDD = 1.89V	9
Deserializer VDDn Supply Current, worst case	IDDR		60	96	mA	VDDn = 1.89V, CL = 8 pF, PCLK = 43 MHz, WORST CASE Pattern, SSCG[3:0] = ON, Default Registers	9
Deserializer VDDIO Supply Current, 1.8V	IDDIOR		21	32	mA	VDDIO = 1.89V, CL = 8 pF, PCLK = 43 MHz, WORST CASE Pattern, Default Registers	9
Deserializer VDDIO Supply Current, 3.3V	IDDIOR		49	83	mA	VDDIO = 3.6V, CL = 8 pF, PCLK = 43 MHz, WORST CASE Pattern, Default Registers	9
Deserializer VDDn Power-down Current	IDDRZ		42	400	µA	VDDn = 1.89V, PDB = 0V; All other LVCMOS Inputs = 0V	9
Deserializer VDDIO Power-down Current 1.8V	IDDIORZ		8	40	µA	VDDIO = 1.89V, PDB = 0V; All other LVCMOS Inputs = 0V	9
Deserializer VDDIO Power-down Current 3.3V	IDDIORZ			800	µA	VDDIO = 3.6V, PDB = 0V; All other LVCMOS Inputs = 0V (typ 350 as extracted, uncertain)	9
Receiver Output Clock Period	tRCP	23.3		100	ns	tRCP = tTCP, PCLK	10
PCLK Duty Cycle	tPDC	45	50	55	%	Default Registers, SSCG[3:0] = OFF	10
LVCMOS Low-to-High Transition Time, PCLK	tCLH	1.3	2	2.8	ns	CL = 8 pF, Default Registers	10
LVCMOS High-to-Low Transition Time, PCLK	tCHL	1.3	2	2.8	ns	CL = 8 pF, Default Registers	10
LVCMOS Low-to-High Transition Time, ROUTn	tCLH	1.6	2.4	3.3	ns	CL = 8 pF, Default Registers	10
LVCMOS High-to-Low Transition Time, ROUTn	tCHL	1.6	2.4	3.3	ns	CL = 8 pF, Default Registers	10
Deserializer Data Lock Time	tDDLT			10	ms	10 MHz-43 MHz, Figure 15	11
Spread Spectrum Clocking Deviation	fdev	-2		2	%	20 MHz-43 MHz, SSC[3:0] = ON (printed ±0.5% to ±2.0%)	11
Spread Spectrum Clocking Modulation Frequency	fmod	9		66	kHz	20 MHz-43 MHz, SSC[3:0] = ON	11
Receiver Input Jitter Tolerance	tRJIT		0.53		UI	43 MHz	11
Input High Level SDA and SCL	VIH	0.7			V	min 0.7 x VDDIO, max VDDIO	13
Input Low Level Voltage SDA and SCL	VIL			0.3	V	max 0.3 x VDDIO	13
I2C Low Level Output Voltage, VDDIO = 3.0V	VOL			0.36	V	SCL and SDA, VDDIO = 3.0V, IOL = 1.5 mA	13
I2C Low Level Output Voltage, VDDIO = 1.71V	VOL			0.36	V	SCL and SDA, VDDIO = 1.71V, IOL = 1 mA	13
I2C Input Current	IIN	-20	1	20	µA	SDA or SCL, Vin = VDDIO or GND	13
I2C Input Pin Capacitance	CIN			5	pF	<5 pF	13
SCL Clock Frequency	fSCL			100	kHz	Deserializer MODE = 0, READ, Register 0x06 b[6:4] = 0x00'h	12

CAD (KiCad official)

Symbol: DS90UB904QSQX
Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
3D model: WQFN-48-EP(7x7) (KiCad packages3D, STEP)
3D model files: ds90ub904qsqx-etched.step / ds90ub904qsqx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds90ub904qsqx.step / ds90ub904qsqx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (46 pp, sha256 05583a291c80f2ba, retrieved 2026-11-02, tier: manufacturer)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

DS90UB904QSQX

Verified DS90UB904QSQX

Verification log 1 record

DS90UB904QSQX

Pinout

Key specifications

Electrical characteristics

CAD (KiCad official)

Provenance