DS90UB902QSQ

{
  "schema_version": 1,
  "type": "component",
  "slug": "ds90ub902qsq",
  "title": "DS90UB902QSQ",
  "brief": "Texas Instruments Serializers / Deserializers, WQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "communication interface chip-uart-485-232",
    "ds90ub902qsq",
    "factory-2.0.0",
    "extractor-text"
  ],
  "component": {
    "mpn": "DS90UB902QSQ",
    "manufacturer": "Texas Instruments",
    "package": "WQFN-40-EP(6x6)",
    "pin_count": 41,
    "category": "Communication Interface Chip/UART/485/232",
    "subcategory": "Serializers / Deserializers",
    "datasheet": "https://www.ti.com/cn/lit/gpn/ds90ub902q-q1",
    "parts": {
      "symbol": "ds90ub902qsq.kicad_sym",
      "footprint": "ds90ub902qsq.kicad_mod",
      "model_3d": "ds90ub902qsq-hero.glb",
      "model_3d_plain": "ds90ub902qsq.glb",
      "model_3d_step": "ds90ub902qsq-etched.step",
      "model_3d_step_plain": "ds90ub902qsq.step",
      "lbr": "ds90ub902qsq.lbr"
    },
    "distributor_links": {
      "lcsc": "C2652193"
    },
    "distributor_check": {
      "checked_at": "2026-10-08T22:54:31Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "no match"
      },
      "mouser": {
        "pn": null,
        "status": "no match"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "ID[x]",
        "type": "input",
        "description": "Device ID address select: a resistor to ground and a 10 kΩ pull-up to the 1.8 V rail set the device ID per Table 4."
      },
      {
        "number": "2",
        "name": "SDA",
        "type": "bidirectional",
        "description": "I²C data line of the bidirectional control bus; open drain, requires an external pull-up resistor to VDDIO."
      },
      {
        "number": "3",
        "name": "SCL",
        "type": "bidirectional",
        "description": "I²C clock line of the bidirectional control bus; open drain, requires an external pull-up resistor to VDDIO."
      },
      {
        "number": "4",
        "name": "VDDSSCG",
        "type": "power_in",
        "description": "1.8 V ±5% supply for the SSCG block, which must be connected whether or not the SSCG function is used."
      },
      {
        "number": "5",
        "name": "PCLK",
        "type": "output",
        "description": "LVCMOS pixel clock output; the strobe edge is set by the RRFB control register."
      },
      {
        "number": "6",
        "name": "VSYNC",
        "type": "output",
        "description": "LVCMOS vertical sync output."
      },
      {
        "number": "7",
        "name": "HSYNC",
        "type": "output",
        "description": "LVCMOS horizontal sync output."
      },
      {
        "number": "8",
        "name": "VDDIO3",
        "type": "power_in",
        "description": "LVTTL I/O buffer power for the single-ended outputs and control inputs; 1.8 V ±5% or 3.3 V ±10%."
      },
      {
        "number": "9",
        "name": "ROUT13",
        "type": "output",
        "description": "LVCMOS parallel data output bit 13."
      },
      {
        "number": "10",
        "name": "ROUT12",
        "type": "output",
        "description": "LVCMOS parallel data output bit 12."
      },
      {
        "number": "11",
        "name": "ROUT11",
        "type": "output",
        "description": "LVCMOS parallel data output bit 11."
      },
      {
        "number": "12",
        "name": "ROUT10",
        "type": "output",
        "description": "LVCMOS parallel data output bit 10."
      },
      {
        "number": "13",
        "name": "VDDD",
        "type": "power_in",
        "description": "1.8 V ±5% digital core power."
      },
      {
        "number": "14",
        "name": "ROUT9",
        "type": "output",
        "description": "LVCMOS parallel data output bit 9."
      },
      {
        "number": "15",
        "name": "ROUT8",
        "type": "output",
        "description": "LVCMOS parallel data output bit 8."
      },
      {
        "number": "16",
        "name": "VDDIO2",
        "type": "power_in",
        "description": "LVTTL I/O buffer power for the single-ended outputs and control inputs; 1.8 V ±5% or 3.3 V ±10%."
      },
      {
        "number": "17",
        "name": "ROUT7",
        "type": "output",
        "description": "LVCMOS parallel data output bit 7."
      },
      {
        "number": "18",
        "name": "ROUT6",
        "type": "output",
        "description": "LVCMOS parallel data output bit 6."
      },
      {
        "number": "19",
        "name": "ROUT5",
        "type": "output",
        "description": "LVCMOS parallel data output bit 5."
      },
      {
        "number": "20",
        "name": "ROUT4",
        "type": "output",
        "description": "LVCMOS parallel data output bit 4."
      },
      {
        "number": "21",
        "name": "ROUT3/GPIO5",
        "type": "bidirectional",
        "description": "Parallel data output bit 3, also configurable as general-purpose I/O GPIO[5]; individually configurable as input or output."
      },
      {
        "number": "22",
        "name": "ROUT[2]/GPIO[4]",
        "type": "bidirectional",
        "description": "Parallel data output bit 2, also configurable as general-purpose I/O GPIO[4]; individually configurable as input or output."
      },
      {
        "number": "23",
        "name": "ROUT[1]/GPIO[3]",
        "type": "bidirectional",
        "description": "Parallel data output bit 1, also configurable as general-purpose I/O GPIO[3]; individually configurable as input or output."
      },
      {
        "number": "24",
        "name": "ROUT[0]/GPIO[2]",
        "type": "bidirectional",
        "description": "Parallel data output bit 0, also configurable as general-purpose I/O GPIO[2]; individually configurable as input or output."
      },
      {
        "number": "25",
        "name": "VDDIO1",
        "type": "power_in",
        "description": "LVTTL I/O buffer power for the single-ended outputs and control inputs; 1.8 V ±5% or 3.3 V ±10%."
      },
      {
        "number": "26",
        "name": "GPIO1",
        "type": "bidirectional",
        "description": "General-purpose LVCMOS I/O pin that can be individually configured as an input or output to control and respond to commands."
      },
      {
        "number": "27",
        "name": "GPIO0",
        "type": "bidirectional",
        "description": "General-purpose LVCMOS I/O pin that can be individually configured as an input or output to control and respond to commands."
      },
      {
        "number": "28",
        "name": "LOCK",
        "type": "output",
        "description": "LOCK status output: high when the CDR/PLL is locked and outputs are active; low when unlocked, and may be used as a link status indicator."
      },
      {
        "number": "29",
        "name": "PDB",
        "type": "input",
        "description": "Power-down input: high enables the deserializer; low puts it in power-down with the PLL shut down and control register data not retained (reset to defaults)."
      },
      {
        "number": "30",
        "name": "VDDR",
        "type": "power_in",
        "description": "1.8 V ±5% analog receiver power."
      },
      {
        "number": "31",
        "name": "PASS",
        "type": "output",
        "description": "BIST-mode output: high indicates error-free transmission, and it asserts low when one or more errors (CRC error on the link) are detected."
      },
      {
        "number": "32",
        "name": "RES/CMLOUTP",
        "type": "output",
        "description": "Non-inverting CML monitor output for the equalized differential signal, enabled via control registers; route to a test point or leave open if unused."
      },
      {
        "number": "33",
        "name": "RES/CMLOUTN",
        "type": "output",
        "description": "Inverting CML monitor output for the equalized differential signal, enabled via control registers; route to a test point or leave open if unused."
      },
      {
        "number": "34",
        "name": "VDDCML",
        "type": "power_in",
        "description": "1.8 V ±5% analog power for the CML and bidirectional channel driver."
      },
      {
        "number": "35",
        "name": "RIN+",
        "type": "bidirectional",
        "description": "Non-inverting FPD-Link III differential input and bidirectional control channel output; the interconnect must be AC coupled with a 100 nF capacitor."
      },
      {
        "number": "36",
        "name": "RIN-",
        "type": "bidirectional",
        "description": "Inverting FPD-Link III differential input and bidirectional control channel output; the interconnect must be AC coupled with a 100 nF capacitor."
      },
      {
        "number": "37",
        "name": "BISTEN",
        "type": "input",
        "description": "BIST enable: high enables BIST mode, low disables BIST mode."
      },
      {
        "number": "38",
        "name": "VDDPLL",
        "type": "power_in",
        "description": "1.8 V ±5% analog PLL power."
      },
      {
        "number": "39",
        "name": "RES",
        "type": "input",
        "description": "Reserved pin that must be tied LOW."
      },
      {
        "number": "40",
        "name": "MODE",
        "type": "input",
        "description": "I²C mode select: low selects master mode (device drives SCL); high selects slave mode (default, device accepts SCL input)."
      },
      {
        "number": "41",
        "name": "EP",
        "type": "passive",
        "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The exposed DAP (thermal/ground pad, shown as VSS DAP, must be grounded, 16 vias) has no printed pin; The page 5 pin table gives ROUT[13:0] only as an ordered pin list (9,10,11,12,14,15,17-24). The mapp; The GPIO[1:0] pin list is 26,27 in the table. Assigning 26 to GPIO1 and 27 to GPIO0 follows the desc",
          "exposed pad 41 added from the footprint"
        ],
        "pages_sent": 15,
        "cost_usd": 0.1194,
        "at": "2026-10-08T22:53:26"
      },
      "datasheet": {
        "url": "https://www.ti.com/cn/lit/gpn/ds90ub902q-q1",
        "pages": 52,
        "sha256": "4d9fc0b46baeeccf",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 41,
        "described": 41,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "ds90ub902qsq.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          6,
          1
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "e5b4286c2329085d9ef7f90d5eb5bf41a435241ecc1baaf1383823b6d6a946ae",
        "checked": "2026-10-08",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "ds90ub902qsq-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          6,
          1
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "ea5aab5eaa11c66b4bec88dbba4b8b840a12e2a5b6430e18b75990deb28613bd",
        "checked": "2026-10-08",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Texas Instruments",
      "Package": "WQFN-40-EP(6x6)",
      "Category": "Communication Interface Chip/UART/485/232",
      "Pins": "41"
    }
  },
  "variants": [],
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "ds90ub902qsq"
  ],
  "discovery_pitch": "DS90UB902QSQ (Texas Instruments) component page: datasheet pinout, KiCad symbol, footprint and 3D.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "ds90ub902qsq.kicad_sym",
    "ds90ub902qsq.kicad_mod",
    "ds90ub902qsq.glb",
    "ds90ub902qsq.step",
    "ds90ub902qsq.lbr",
    "docs/hero.png",
    "docs/ds90ub902qsq-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "ds90ub902qsq-hero.glb",
    "ds90ub902qsq-hero.overlay.json"
  ],
  "visibility": {
    "public": true
  }
}