component
DS90UB902QSQ
Public Made by Adomby adom
Texas Instruments Serializers / Deserializers, WQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownDS90UB902QSQ
Texas Instruments · Serializers / Deserializers · WQFN-40-EP(6x6)
DS90UB902QSQ from Texas Instruments, in a WQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ID[x] | input | Device ID address select: a resistor to ground and a 10 kΩ pull-up to the 1.8 V rail set the device ID per Table 4. |
| 2 | SDA | bidirectional | I²C data line of the bidirectional control bus; open drain, requires an external pull-up resistor to VDDIO. |
| 3 | SCL | bidirectional | I²C clock line of the bidirectional control bus; open drain, requires an external pull-up resistor to VDDIO. |
| 4 | VDDSSCG | power_in | 1.8 V ±5% supply for the SSCG block, which must be connected whether or not the SSCG function is used. |
| 5 | PCLK | output | LVCMOS pixel clock output; the strobe edge is set by the RRFB control register. |
| 6 | VSYNC | output | LVCMOS vertical sync output. |
| 7 | HSYNC | output | LVCMOS horizontal sync output. |
| 8 | VDDIO3 | power_in | LVTTL I/O buffer power for the single-ended outputs and control inputs; 1.8 V ±5% or 3.3 V ±10%. |
| 9 | ROUT13 | output | LVCMOS parallel data output bit 13. |
| 10 | ROUT12 | output | LVCMOS parallel data output bit 12. |
| 11 | ROUT11 | output | LVCMOS parallel data output bit 11. |
| 12 | ROUT10 | output | LVCMOS parallel data output bit 10. |
| 13 | VDDD | power_in | 1.8 V ±5% digital core power. |
| 14 | ROUT9 | output | LVCMOS parallel data output bit 9. |
| 15 | ROUT8 | output | LVCMOS parallel data output bit 8. |
| 16 | VDDIO2 | power_in | LVTTL I/O buffer power for the single-ended outputs and control inputs; 1.8 V ±5% or 3.3 V ±10%. |
| 17 | ROUT7 | output | LVCMOS parallel data output bit 7. |
| 18 | ROUT6 | output | LVCMOS parallel data output bit 6. |
| 19 | ROUT5 | output | LVCMOS parallel data output bit 5. |
| 20 | ROUT4 | output | LVCMOS parallel data output bit 4. |
| 21 | ROUT3/GPIO5 | bidirectional | Parallel data output bit 3, also configurable as general-purpose I/O GPIO[5]; individually configurable as input or output. |
| 22 | ROUT[2]/GPIO[4] | bidirectional | Parallel data output bit 2, also configurable as general-purpose I/O GPIO[4]; individually configurable as input or output. |
| 23 | ROUT[1]/GPIO[3] | bidirectional | Parallel data output bit 1, also configurable as general-purpose I/O GPIO[3]; individually configurable as input or output. |
| 24 | ROUT[0]/GPIO[2] | bidirectional | Parallel data output bit 0, also configurable as general-purpose I/O GPIO[2]; individually configurable as input or output. |
| 25 | VDDIO1 | power_in | LVTTL I/O buffer power for the single-ended outputs and control inputs; 1.8 V ±5% or 3.3 V ±10%. |
| 26 | GPIO1 | bidirectional | General-purpose LVCMOS I/O pin that can be individually configured as an input or output to control and respond to commands. |
| 27 | GPIO0 | bidirectional | General-purpose LVCMOS I/O pin that can be individually configured as an input or output to control and respond to commands. |
| 28 | LOCK | output | LOCK status output: high when the CDR/PLL is locked and outputs are active; low when unlocked, and may be used as a link status indicator. |
| 29 | PDB | input | Power-down input: high enables the deserializer; low puts it in power-down with the PLL shut down and control register data not retained (reset to defaults). |
| 30 | VDDR | power_in | 1.8 V ±5% analog receiver power. |
| 31 | PASS | output | BIST-mode output: high indicates error-free transmission, and it asserts low when one or more errors (CRC error on the link) are detected. |
| 32 | RES/CMLOUTP | output | Non-inverting CML monitor output for the equalized differential signal, enabled via control registers; route to a test point or leave open if unused. |
| 33 | RES/CMLOUTN | output | Inverting CML monitor output for the equalized differential signal, enabled via control registers; route to a test point or leave open if unused. |
| 34 | VDDCML | power_in | 1.8 V ±5% analog power for the CML and bidirectional channel driver. |
| 35 | RIN+ | bidirectional | Non-inverting FPD-Link III differential input and bidirectional control channel output; the interconnect must be AC coupled with a 100 nF capacitor. |
| 36 | RIN- | bidirectional | Inverting FPD-Link III differential input and bidirectional control channel output; the interconnect must be AC coupled with a 100 nF capacitor. |
| 37 | BISTEN | input | BIST enable: high enables BIST mode, low disables BIST mode. |
| 38 | VDDPLL | power_in | 1.8 V ±5% analog PLL power. |
| 39 | RES | input | Reserved pin that must be tied LOW. |
| 40 | MODE | input | I²C mode select: low selects master mode (device drives SCL); high selects slave mode (default, device accepts SCL input). |
| 41 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-40-EP(6x6) |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 41 |
CAD (KiCad official)
- Symbol:
DS90UB902QSQ - Footprint:
Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm - 3D model: WQFN-40-EP(6x6) (KiCad packages3D, STEP)
- 3D model files:
ds90ub902qsq-etched.step/ds90ub902qsq-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ds90ub902qsq.step/ds90ub902qsq.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (52 pp, sha256
4d9fc0b46baeeccf, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).