component
DS8570F8
Public Made by Adomby adom
DSTECH Linear Voltage Regulators (LDO), ESOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 2d ago |
| viewers | 2d ago |
| ds8570f8-etched.glb | 2d ago |
| ds8570f8-etched.step | 2d ago |
| ds8570f8-hero.glb | 2d ago |
| ds8570f8-hero.overlay.json | 2d ago |
| ds8570f8.glb | 2d ago |
| ds8570f8.kicad_mod | 2d ago |
| ds8570f8.kicad_sym | 2d ago |
| ds8570f8.lbr | 2d ago |
| ds8570f8.step | 2d ago |
| package.json | 2d ago |
| page.json | 2d ago |
| README.md | 2d ago |
| verification.json | 2d ago |
DS8570F8
DSTECH · Linear Voltage Regulators (LDO) · ESOP-8
DS8570F8 from DSTECH, in a ESOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | POK | output | Power good open-drain output that goes high once VOUT reaches 90% of its normal value; it needs a 100kΩ pull-up resistor to VOUT. |
| 2 | EN | input | Enable control input with logic-high VIH of at least 1.2V and logic-low VIL of at most 0.4V; the regulator is off when EN is low or floating because EN is pulled low internally. |
| 3 | VIN | power_in | Input supply voltage with a stated range of 1V to 5.5V; a 10uF or larger input capacitor placed as close to the IC as possible is recommended. |
| 4 | VCC | power_in | Supply voltage for the control circuit, 3V to 5.5V, which must stay above VOUT + 1.5V. |
| 5 | NC | unconnected | No internal connection. |
| 6 | VOUT | power_out | Regulated output voltage, adjustable from 0.8V up to VIN through the FB divider, with output current up to 3A. |
| 7 | FB | input | Feedback input for output voltage setting, where VOUT = VREF × (R1+R2)/R2 with VREF of 0.8V typical and R1 and R2 each above 10kΩ. |
| 8 | GND | power_in | Ground reference for the device. |
| 9 | GND | power_in | The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | DSTECH |
| Package | ESOP-8 |
| Category | Power Management ICs |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN & VCC to GND | -0.3 | 6 | V | 4 | |||
| VOUT to GND | -0.3 | 6 | V | 4 | |||
| Other to GND | -0.3 | 6 | V | 4 | |||
| Lead Temperature (Soldering, 10 sec.) | 260 | °C | 10 sec soldering | 4 | |||
| Junction Temperature | 150 | °C | 4 | ||||
| Storage Temperature Range | -60 | 150 | °C | 4 | |||
| ESD Susceptibility HBM | 2 | KV | HBM | 4 | |||
| Control Voltage, VCC | VCC | 3 | 5.5 | V | VCC > VOUT + 1.5V | 4 | |
| Input Voltage | VIN | 1 | 5.5 | V | 4 | ||
| Junction Temperature Range | -40 | 125 | °C | 4 | |||
| Ambient Temperature Range | -40 | 85 | °C | 4 | |||
| VCC Operation Range | VDD | 3 | 5.5 | V | 5 | ||
| VCC POR Threshold | VPOR_VCC | 2.4 | 2.7 | 3 | V | VCC Rising | 5 |
| VCC POR Falling Hysteresis | VPOR_VCC | 0.15 | 0.2 | V | VCC Falling | 5 | |
| Quiescent Current | IQ | 0.6 | 1.2 | mA | EN on, no load | 5 | |
| Input Voltage Range | VIN | 1 | 5.5 | V | 5 | ||
| VIN POR Threshold | VPOR_VIN | 0.7 | 0.8 | 0.9 | V | VIN Rising | 5 |
| VIN POR Falling Hysteresis | VPOR_VIN | 0.15 | 0.2 | 0.25 | V | VIN Falling | 5 |
| Reference Voltage | VREF | 0.788 | 0.8 | 0.812 | V | 5 | |
| VOUT Load Regulation | VLOAD | 0.5 | 1 | % | IOUT = 1mA to 3A, VIN = VOUT + 1V | 5 | |
| OUT Line Regulation | VLINE | 0.2 | 0.6 | % | VCC = 3.6V to 5.5V, VIN = VOUT + 1V to 5V, IOUT = 1mA | 5 | |
| Dropout Voltage | VDROP | 250 | 350 | mV | IOUT = 2A | 5 | |
| Dropout Voltage | VDROP | 350 | 450 | mV | IOUT = 3A | 5 | |
| Current Limit | ILIM | 3.1 | 3.6 | 4.2 | A | VIN = 3.6V | 5 |
| Short Circuit Current | ISC | 1 | 1.4 | 1.8 | A | VOUT < 0.2V | 5 |
| POK Delay Time | 1 | 1.5 | mS | 5 | |||
| POK Sink Capability | VPOK | 0.2 | 0.4 | V | ISINK = 10mA | 5 | |
| EN Input Voltage Logic-High | VIH | 1.2 | V | 5 | |||
| EN Input Voltage Logic-Low | VIL | 0.4 | V | 5 | |||
| EN Delay Time | 0.3 | 0.85 | 1.4 | mS | 5 | ||
| VDD Pin Shutdown Current | ISHDN_VDD | 1 | uA | VEN = 0V | 6 | ||
| VIN Pin Shutdown Current | ISHDN_VIN | 1 | uA | VEN = 0V, VIN = 5V | 6 | ||
| Soft-Start Time | TSS | 1.9 | 2.8 | 3.75 | mS | 6 | |
| Package Thermal Resistance, ESOP-8 junction-to-ambient | θJA | 75 | °C/W | 4 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | capacitors must be back to the DS8570 ground pin using as wide and as short of a copper trace as is practical. | 9 |
CAD (KiCad official)
- Symbol:
DS8570F8 - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm - 3D model: ESOP-8 (KiCad packages3D, STEP)
- 3D model files:
ds8570f8-etched.step/ds8570f8-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ds8570f8.step/ds8570f8.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: DSTECH datasheet (11 pp, sha256
fb0319560326929d, retrieved 2026-11-04, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).