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DS8561-36S3

Public Made by Adom

by adom

DSTECH Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT23-3. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DS8561-36S3

DSTECH · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT23-3

DS8561-36S3 from DSTECH, in a SOT23-3. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground pin; the input and output capacitor ground connections must be returned to this pin using short, wide traces.
2 VOUT power_out Regulated output voltage port; an output capacitor of 1uF to 22uF with ESR above 1mΩ should be placed close to VOUT and GND.
3 VIN power_in Power input port with a 1.2V to 5.5V input range; an input capacitor of at least 1uF should be placed close to VIN and GND.

Key specifications

Parameter Value
Manufacturer DSTECH
Package SOT23-3
Category Power Management (PMIC)
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage VIN 1.2 5.5 V 7
Output voltage accuracy -2 2 % ILOAD = 0.1mA 7
Output current limit ILIM 301 600 mA VOUT = 0V 7
Shutdown current ISD 0.1 0.5 μA VEN = 0V, VOUT = 0V 7
EN input current IEN 10 100 nA VEN = 5V 7
VIN to GND -0.3 7 V 6
VOUT, EN to GND -0.3 6 V 6
VOUT to VIN -6 0.3 V 6
ESD HBM 2 KV 6
ESD MM 200 V 6
ESD CDM 2 KV 6
Soldering temperature 260 °C Soldering, 10 sec. 6
Junction temperature 150 °C 6
Storage temperature range -60 150 °C 6
Thermal resistance junction-to-ambient, SOT-23-3 θJA 200 °C/W TA = 25°C, DSTECH EVB board (Note 2) 6
Recommended input voltage VIN 1.2 5.5 V 6
Application junction temperature range -40 125 °C 6
Application ambient temperature range -40 85 °C 6

CAD (KiCad official)

  • Symbol: DS8561-36S3
  • Footprint: Package_TO_SOT_SMD:SOT-23-3
  • 3D model: SOT23-3 (KiCad packages3D, STEP)
  • 3D model files: ds8561-36s3-etched.step / ds8561-36s3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds8561-36s3.step / ds8561-36s3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: DSTECH datasheet (19 pp, sha256 b28c6b5e18533c57, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF