# DS40MB200SQ

**Texas Instruments** · Signal Buffers, Repeaters, Splitters · WQFN-48-EP(7x7)

DS40MB200SQ from Texas Instruments, in a WQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PREL_1 | input | 3.3V LVCMOS pre-emphasis level select bit 1 for line-side drivers (LO_0+/- and LO_1+/-). Internally pulled up. Combined with PREL_0 to choose one of four pre-emphasis levels (see PRE_L emphasis table). |
| 2 | VCC | power_in | 3.3V +/-5% supply. Each VCC pin should connect to the VCC plane through a low-inductance via close to the pin; TI recommends a 0.01uF and 0.1uF X7R 0402 bypass capacitor between each VCC pin and ground. |
| 3 | SOB_0- | output | Switch-side B multiplexer 0 inverting CML differential output. Has an internal 50 ohm resistor to VCC. Must be AC-coupled. |
| 4 | SOB_0+ | output | Switch-side B multiplexer 0 non-inverting CML differential output. Has an internal 50 ohm resistor to VCC. Must be AC-coupled. |
| 5 | GND | power_in | Reference ground. Each GND pin must connect to the ground plane through a low-inductance path (typically a via near the pin). |
| 6 | LI_0+ | input | Line-side port 0 non-inverting CML differential input. Has an internal 50 ohm resistor to an internal reference voltage. Must be AC-coupled (see Figure 7-1). |
| 7 | LI_0- | input | Line-side port 0 inverting CML differential input. Has an internal 50 ohm resistor to an internal reference voltage. Must be AC-coupled. |
| 8 | VCC | power_in | 3.3V +/-5% supply. Bypass to ground with 0.01uF and 0.1uF X7R 0402 capacitors close to the pin. |
| 9 | LO_1+ | output | Line-side port 1 non-inverting CML differential output. Has an internal 50 ohm resistor to VCC. Must be AC-coupled. |
| 10 | LO_1- | output | Line-side port 1 inverting CML differential output. Has an internal 50 ohm resistor to VCC. Must be AC-coupled. |
| 11 | GND | power_in | Reference ground. Low-inductance via to the ground plane recommended. |
| 12 | PREL_0 | input | 3.3V LVCMOS pre-emphasis level select bit 0 for line-side drivers (LO_0+/- and LO_1+/-). Internally pulled up. Combined with PREL_1 to select one of four pre-emphasis levels. |
| 13 | MUX_S1 | input | 3.3V LVCMOS multiplexer 1 select: logic high selects switch B for MUX 1. Internally pulled up. Default state of MUX 1 is switch A. |
| 14 | VCC | power_in | 3.3V +/-5% supply. Bypass with 0.01uF and 0.1uF X7R 0402 close to the pin. |
| 15 | SIA_1- | input | Switch-side A multiplexer 1 inverting CML differential input. Has an internal 50 ohm resistor to an internal reference voltage. Must be AC-coupled. |
| 16 | SIA_1+ | input | Switch-side A multiplexer 1 non-inverting CML differential input. Has an internal 50 ohm resistor to an internal reference voltage. Must be AC-coupled. |
| 17 | GND | power_in | Reference ground. Low-inductance via to the ground plane recommended. |
| 18 | SIB_1- | input | Switch-side B multiplexer 1 inverting CML differential input. Has an internal 50 ohm resistor to an internal reference voltage. Must be AC-coupled. |
| 19 | SIB_1+ | input | Switch-side B multiplexer 1 non-inverting CML differential input. Has an internal 50 ohm resistor to an internal reference voltage. Must be AC-coupled. |
| 20 | VCC | power_in | 3.3V +/-5% supply. Bypass with 0.01uF and 0.1uF X7R 0402 close to the pin. |
| 21 | SOA_1- | output | Switch-side A multiplexer 1 inverting CML differential output. Has an internal 50 ohm resistor to VCC. |
| 22 | SOA_1+ | output | Switch-side A multiplexer 1 non-inverting CML differential output. Has an internal 50 ohm resistor to VCC. |
| 23 | LB1A | input | 3.3V LVCMOS. A logic low at LB1A enables the internal loopback path from SIA_1+/- back to SOA_1+/-. Internally pulled up. |
| 24 | LB1B | input | 3.3V LVCMOS. A logic low at LB1B enables the internal loopback path from SIB_1+/- back to SOA_1+/-. Internally pulled up. |
| 25 | PRES_1 | input | 3.3V LVCMOS pre-emphasis level select bit 1 for switch-side drivers (SOA_0+/-, SOB_0+/-, SOA_1+/-, SOB_1+/-). Internally pulled up. Combined with PRES_0 to choose one of four pre-emphasis levels. |
| 26 | RSV | input | Reserved pin used for factory test. May be left open, connected to GND, or tied to GND through an external pull-down resistor. |
| 27 | SOB_1- | output | Switch-side B multiplexer 1 inverting CML differential output. Has an internal 50 ohm resistor to VCC. |
| 28 | SOB_1+ | output | Switch-side B multiplexer 1 non-inverting CML differential output. Has an internal 50 ohm resistor to VCC. |
| 29 | VCC | power_in | 3.3V +/-5% supply. Bypass with 0.01uF and 0.1uF X7R 0402 close to the pin. |
| 30 | LI_1+ | input | Line-side port 1 non-inverting CML differential input. Has an internal 50 ohm resistor to an internal reference voltage. Must be AC-coupled. |
| 31 | LI_1- | input | Line-side port 1 inverting CML differential input. Has an internal 50 ohm resistor to an internal reference voltage. Must be AC-coupled. |
| 32 | GND | power_in | Reference ground. Low-inductance via to the ground plane recommended. |
| 33 | LO_0+ | output | Line-side port 0 non-inverting CML differential output. Has an internal 50 ohm resistor to VCC. Must be AC-coupled. |
| 34 | LO_0- | output | Line-side port 0 inverting CML differential output. Has an internal 50 ohm resistor to VCC. Must be AC-coupled. |
| 35 | VCC | power_in | 3.3V +/-5% supply. Bypass with 0.01uF and 0.1uF X7R 0402 close to the pin. |
| 36 | PRES_0 | input | 3.3V LVCMOS pre-emphasis level select bit 0 for switch-side drivers (SOA_0+/-, SOB_0+/-, SOA_1+/-, SOB_1+/-). Internally pulled up. Combined with PRES_1 to select one of four pre-emphasis levels. |
| 37 | MUX_S0 | input | 3.3V LVCMOS multiplexer 0 select: logic high selects switch B for MUX 0. Internally pulled up. Default state of MUX 0 is switch A. |
| 38 | VCC | power_in | 3.3V +/-5% supply. Bypass with 0.01uF and 0.1uF X7R 0402 close to the pin. |
| 39 | SIA_0- | input | Switch-side A multiplexer 0 inverting CML differential input. Has an internal 50 ohm resistor to an internal reference voltage. Must be AC-coupled. |
| 40 | SIA_0+ | input | Switch-side A multiplexer 0 non-inverting CML differential input. Has an internal 50 ohm resistor to an internal reference voltage. Must be AC-coupled. |
| 41 | GND | power_in | Reference ground. Low-inductance via to the ground plane recommended. |
| 42 | SIB_0- | input | Switch-side B multiplexer 0 inverting CML differential input. Has an internal 50 ohm resistor to an internal reference voltage. Must be AC-coupled. |
| 43 | SIB_0+ | input | Switch-side B multiplexer 0 non-inverting CML differential input. Has an internal 50 ohm resistor to an internal reference voltage. Must be AC-coupled. |
| 44 | VCC | power_in | 3.3V +/-5% supply. Bypass with 0.01uF and 0.1uF X7R 0402 close to the pin. |
| 45 | SOA_0- | output | Switch-side A multiplexer 0 inverting CML differential output. Has an internal 50 ohm resistor to VCC. |
| 46 | SOA_0+ | output | Switch-side A multiplexer 0 non-inverting CML differential output. Has an internal 50 ohm resistor to VCC. |
| 47 | LB0A | input | 3.3V LVCMOS. A logic low at LB0A enables the internal loopback path from SIA_0+/- back to SOA_0+/-. Internally pulled up. |
| 48 | LB0B | input | 3.3V LVCMOS. A logic low at LB0B enables the internal loopback path from SIB_0+/- back to SOA_0+/-. Internally pulled up. |
| DAP | GND | power_in | Die attach pad (exposed metal pad on the bottom, center of WQFN-48). Must be connected to the GND plane through at least four vias to lower ground impedance and improve thermal performance. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-48-EP(7x7) |
| Category | Interface |
| Pins | 49 |

## Ordering variants

Same part, different packaging or reel option.

- `DS40MB200SQ`
- `DS40MB200SQE`
- `DS40MB200SQX`

## CAD (KiCad official)

- Symbol: `DS40MB200SQ`
- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`
- 3D model: WQFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files: `ds40mb200sq-etched.step` / `ds40mb200sq-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ds40mb200sq.step` / `ds40mb200sq.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ds40mb200) (25 pp, sha256 `a347064cd35ec67a`, retrieved 2026-08-17, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ds40mb200sq-datasheet.pdf)