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DS25BR440TSQX

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Texas Instruments LVDS ICs, WQFN-40(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DS25BR440TSQX

Texas Instruments · LVDS ICs · WQFN-40(6x6)

DS25BR440TSQX from Texas Instruments, in a WQFN-40(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN0+ input Non-inverting high speed LVDS input of channel 0 with internal 100Ω termination between IN0+ and IN0-.
2 IN0- input Inverting high speed LVDS input of channel 0 with internal 100Ω termination between IN0+ and IN0-.
3 VDD power_in Power supply pin, 3.0V to 3.6V recommended operating range.
4 IN1+ input Non-inverting high speed LVDS input of channel 1 with internal 100Ω termination between IN1+ and IN1-.
5 IN1- input Inverting high speed LVDS input of channel 1 with internal 100Ω termination between IN1+ and IN1-.
6 IN2+ input Non-inverting high speed LVDS input of channel 2 with internal 100Ω termination between IN2+ and IN2-.
7 IN2- input Inverting high speed LVDS input of channel 2 with internal 100Ω termination between IN2+ and IN2-.
8 VDD power_in Power supply pin, 3.0V to 3.6V recommended operating range.
9 IN3+ input Non-inverting high speed LVDS input of channel 3 with internal 100Ω termination between IN3+ and IN3-.
10 IN3- input Inverting high speed LVDS input of channel 3 with internal 100Ω termination between IN3+ and IN3-.
11 EQ2 input LVCMOS receive equalization select for input IN2; 0 = OFF, 1 = ON.
12 EQ3 input LVCMOS receive equalization select for input IN3; 0 = OFF, 1 = ON.
13 LOS3 output Open drain LVCMOS loss-of-signal output reporting an open input fault at IN3; requires an external pull-up resistor.
14 LOS0 output Open drain LVCMOS loss-of-signal output reporting an open input fault at IN0; requires an external pull-up resistor.
15 VDD power_in Power supply pin, 3.0V to 3.6V recommended operating range.
16 GND power_in Ground pin.
17 NC unconnected No connect pin that may be left floating.
18 PE3 input LVCMOS transmit pre-emphasis select for output OUT3; 0 = OFF, 1 = ON.
19 PE2 input LVCMOS transmit pre-emphasis select for output OUT2; 0 = OFF, 1 = ON.
20 PE1 input LVCMOS transmit pre-emphasis select for output OUT1; 0 = OFF, 1 = ON.
21 OUT3- output Inverting high speed LVDS output of channel 3 with internal 100Ω termination between OUT3+ and OUT3-.
22 OUT3+ output Non-inverting high speed LVDS output of channel 3 with internal 100Ω termination between OUT3+ and OUT3-.
23 OUT2- output Inverting high speed LVDS output of channel 2 with internal 100Ω termination between OUT2+ and OUT2-.
24 OUT2+ output Non-inverting high speed LVDS output of channel 2 with internal 100Ω termination between OUT2+ and OUT2-.
25 VDD power_in Power supply pin, 3.0V to 3.6V recommended operating range.
26 OUT1- output Inverting high speed LVDS output of channel 1 with internal 100Ω termination between OUT1+ and OUT1-.
27 OUT1+ output Non-inverting high speed LVDS output of channel 1 with internal 100Ω termination between OUT1+ and OUT1-.
28 OUT0- output Inverting high speed LVDS output of channel 0 with internal 100Ω termination between OUT0+ and OUT0-.
29 OUT0+ output Non-inverting high speed LVDS output of channel 0 with internal 100Ω termination between OUT0+ and OUT0-.
30 VDD power_in Power supply pin, 3.0V to 3.6V recommended operating range.
31 PE0 input LVCMOS transmit pre-emphasis select for output OUT0; 0 = OFF, 1 = ON.
32 PWDN3 input LVCMOS channel 3 output power down; low puts OUT3 in power down while the LOS circuitry on IN3 stays enabled.
33 PWDN2 input LVCMOS channel 2 output power down; low puts OUT2 in power down while the LOS circuitry on IN2 stays enabled.
34 PWDN1 input LVCMOS channel 1 output power down; low puts OUT1 in power down while the LOS circuitry on IN1 stays enabled.
35 PWDN0 input LVCMOS channel 0 output power down; low puts OUT0 in power down while the LOS circuitry on IN0 stays enabled.
36 LOS2 output Open drain LVCMOS loss-of-signal output reporting an open input fault at IN2; requires an external pull-up resistor.
37 LOS1 output Open drain LVCMOS loss-of-signal output reporting an open input fault at IN1; requires an external pull-up resistor.
38 PWDN input LVCMOS device power down; low puts the device in power down mode and also disables the LOS circuitry.
39 EQ1 input LVCMOS receive equalization select for input IN1; 0 = OFF, 1 = ON.
40 EQ0 input LVCMOS receive equalization select for input IN0; 0 = OFF, 1 = ON.
41 DAP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-40(6x6)
Category Communication Interface Chip
Pins 41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VCC 3 3.3 3.6 V 4
Receiver Differential Input Voltage VID 0 1 V 4
Operating Free Air Temperature TA -40 25 85 °C 4
Supply Voltage (abs max) VCC -0.3 4 V 4
LVDS Input Voltage -0.3 4 V 4
Differential Input Voltage /VID/ 1 V 4
LVDS Differential Output Voltage 0 1 V 4
Junction Temperature 150 °C 4
Storage Temperature Range -65 150 °C 4
Lead Temperature 260 °C Soldering (4 sec.) 4
Maximum Package Power Dissipation 2.44 W at 25°C, RTA0040A package 4
Junction-to-ambient thermal resistance θJA 26.9 °C/W 4
Junction-to-case thermal resistance θJC 3.8 °C/W 4
High Level Input Voltage VIH 2 3.6 V max = VDD 4
Low Level Input Voltage VIL 0 0.8 V min = GND 4
High Level Input Current IIH -10 0 10 μA VIN = 3.6V, VCC = 3.6V 4
Low Level Input Current IIL -10 0 10 μA VIN = GND, VCC = 3.6V 5
Input Clamp Voltage VCL -0.9 -1.5 V ICL = −18 mA, VCC = 0V 5
Low Level Output Voltage VOL 0.26 0.4 V IOL= 4 mA 5
Input Differential Voltage VID 0 1 V 5
Differential Input High Threshold VTH 0 100 mV VCM = +0.05V or VCC-0.05V 5
Differential Input Low Threshold VTL -100 0 mV VCM = +0.05V or VCC-0.05V 5
Input Current IIN -10 1 10 μA VIN = +3.6V or 0V, VCC = 3.6V or 0V 5
Differential Output Voltage VOD 250 350 450 mV RL = 100Ω 5
Change in Magnitude of VOD ΔVOD -35 35 mV RL = 100Ω 5
Offset Voltage VOS 1.05 1.2 1.375 V RL = 100Ω 5
Change in Magnitude of VOS ΔVOS -35 35 mV RL = 100Ω 5
Output Short Circuit Current IOS -35 -55 mA OUT to GND 5
Output Short Circuit Current IOS 7 55 mA OUT to VCC 5
Supply Current ICC 162 190 mA PE = OFF, EQ = OFF, PWDN = H 5
Power Down Supply Current ICCZ 55 63 mA PWDN = L 5
Differential Propagation Delay Low to High tPLHD 390 600 ps RL = 100Ω 5
Differential Propagation Delay High to Low tPHLD 400 600 ps RL = 100Ω 5
Pulse Skew tSKD1 10 50 ps RL = 100Ω 5
Channel to Channel Skew tSKD2 18 65 ps RL = 100Ω 6
Part to Part Skew tSKD3 50 170 ps RL = 100Ω 6
Rise Time tLHT 80 160 ps RL = 100Ω 6
Fall Time tHLT 80 160 ps RL = 100Ω 6
Any PWDN to Output Active Time tON 8 20 μs 6
Any PWDN to Output Inactive Time tOFF 5 12 ns 6
Random Jitter (RMS) EQ/PE off tRJ2 0.5 1 ps VID = 350 mV, VCM = 1.2V, Clock 3.125 Gbps, no test channels 6
Deterministic Jitter (p-p) EQ/PE off tDJ2 10 29 ps VID = 350 mV, VCM = 1.2V, K28.5 3.125 Gbps, no test channels 6
Total Jitter (p-p) EQ/PE off tTJ2 0.06 0.14 UIP-P VID = 350 mV, VCM = 1.2V, PRBS-23 3.125 Gbps, no test channels 6
Input Capacitance CIN 1.7 pF Any LVDS Input Pin to GND 5
Output Capacitance COUT 1.2 pF Any LVDS Output Pin to GND 5
Input Termination Resistor RIN 100 Ω Between IN+ and IN- 5
Output Termination Resistor ROUT 100 Ω Between OUT+ and OUT- 5

CAD (KiCad official)

  • Symbol: DS25BR440TSQX
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: WQFN-40(6x6) (KiCad packages3D, STEP)
  • 3D model files: ds25br440tsqx-etched.step / ds25br440tsqx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds25br440tsqx.step / ds25br440tsqx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (21 pp, sha256 a0c2d1b73307a048, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF