component
DS25BR204TSQ
Public Made by Adomby adom
Texas Instruments LVDS ICs, WQFN-40(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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"schema_version": 1,
"type": "component",
"slug": "ds25br204tsq",
"title": "DS25BR204TSQ",
"brief": "Texas Instruments LVDS ICs, WQFN-40(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"version": "0.1.0",
"license": "CC-BY-SA-4.0",
"tags": [
"component",
"interface",
"ds25br204tsq",
"factory-2.0.0",
"extractor-text"
],
"component": {
"mpn": "DS25BR204TSQ",
"manufacturer": "Texas Instruments",
"package": "WQFN-40(6x6)",
"pin_count": 41,
"category": "Interface",
"subcategory": "LVDS ICs",
"datasheet": "https://www.ti.com/cn/lit/gpn/ds25br204",
"parts": {
"symbol": "ds25br204tsq.kicad_sym",
"footprint": "ds25br204tsq.kicad_mod",
"model_3d": "ds25br204tsq-hero.glb",
"model_3d_plain": "ds25br204tsq.glb",
"model_3d_step": "ds25br204tsq-etched.step",
"model_3d_step_plain": "ds25br204tsq.step",
"lbr": "ds25br204tsq.lbr"
},
"distributor_links": {
"lcsc": "C2652392"
},
"distributor_check": {
"checked_at": "2026-10-11T07:26:32Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": null,
"status": "no match"
},
"mouser": {
"pn": null,
"status": "no match"
}
},
"pins": [
{
"number": "1",
"name": "NC",
"type": "unconnected",
"description": "No-connect pin; may be left floating."
},
{
"number": "2",
"name": "NC",
"type": "unconnected",
"description": "No-connect pin; may be left floating."
},
{
"number": "3",
"name": "VDD",
"type": "power_in",
"description": "Power supply pin; the device is specified for VCC of 3.0 V to 3.6 V (3.3 V typical)."
},
{
"number": "4",
"name": "IN1+",
"type": "input",
"description": "Non-inverting high-speed LVDS input 1, internally terminated with 100 Ω between IN1+ and IN1-, accepting LVDS, CML and LVPECL levels."
},
{
"number": "5",
"name": "IN1-",
"type": "input",
"description": "Inverting high-speed LVDS input 1, internally terminated with 100 Ω between IN1+ and IN1-."
},
{
"number": "6",
"name": "IN2+",
"type": "input",
"description": "Non-inverting high-speed LVDS input 2, internally terminated with 100 Ω between IN2+ and IN2-, accepting LVDS, CML and LVPECL levels."
},
{
"number": "7",
"name": "IN2-",
"type": "input",
"description": "Inverting high-speed LVDS input 2, internally terminated with 100 Ω between IN2+ and IN2-."
},
{
"number": "8",
"name": "VDD",
"type": "power_in",
"description": "Power supply pin; the device is specified for VCC of 3.0 V to 3.6 V (3.3 V typical)."
},
{
"number": "9",
"name": "NC",
"type": "unconnected",
"description": "No-connect pin; may be left floating."
},
{
"number": "10",
"name": "NC",
"type": "unconnected",
"description": "No-connect pin; may be left floating."
},
{
"number": "11",
"name": "EQ2",
"type": "input",
"description": "LVCMOS receive equalization level select for input IN2; logic 0 sets equalization OFF and logic 1 sets it ON."
},
{
"number": "12",
"name": "NC",
"type": "unconnected",
"description": "No-connect pin; may be left floating."
},
{
"number": "13",
"name": "NC",
"type": "unconnected",
"description": "No-connect pin; may be left floating."
},
{
"number": "14",
"name": "SEL_in",
"type": "input",
"description": "LVCMOS input select pin; logic 0 selects IN1 and logic 1 selects IN2."
},
{
"number": "15",
"name": "VDD",
"type": "power_in",
"description": "Power supply pin; the device is specified for VCC of 3.0 V to 3.6 V (3.3 V typical)."
},
{
"number": "16",
"name": "GND",
"type": "power_in",
"description": "Ground pin; the device ground, which is also connected to the exposed die attach pad (DAP)."
},
{
"number": "17",
"name": "NC",
"type": "unconnected",
"description": "No-connect pin; may be left floating."
},
{
"number": "18",
"name": "PE3",
"type": "input",
"description": "LVCMOS transmit pre-emphasis level select for output OUT3; logic 0 sets pre-emphasis OFF and logic 1 sets it ON."
},
{
"number": "19",
"name": "PE2",
"type": "input",
"description": "LVCMOS transmit pre-emphasis level select for output OUT2; logic 0 sets pre-emphasis OFF and logic 1 sets it ON."
},
{
"number": "20",
"name": "PE1",
"type": "input",
"description": "LVCMOS transmit pre-emphasis level select for output OUT1; logic 0 sets pre-emphasis OFF and logic 1 sets it ON."
},
{
"number": "21",
"name": "OUT3-",
"type": "output",
"description": "Inverting high-speed LVDS output 3, compliant with the LVDS standard with an internal 100 Ω termination between OUT3+ and OUT3-."
},
{
"number": "22",
"name": "OUT3+",
"type": "output",
"description": "Non-inverting high-speed LVDS output 3, compliant with the LVDS standard with an internal 100 Ω termination between OUT3+ and OUT3-."
},
{
"number": "23",
"name": "OUT2-",
"type": "output",
"description": "Inverting high-speed LVDS output 2, compliant with the LVDS standard with an internal 100 Ω termination between OUT2+ and OUT2-."
},
{
"number": "24",
"name": "OUT2+",
"type": "output",
"description": "Non-inverting high-speed LVDS output 2, compliant with the LVDS standard with an internal 100 Ω termination between OUT2+ and OUT2-."
},
{
"number": "25",
"name": "VDD",
"type": "power_in",
"description": "Power supply pin; the device is specified for VCC of 3.0 V to 3.6 V (3.3 V typical)."
},
{
"number": "26",
"name": "OUT1-",
"type": "output",
"description": "Inverting high-speed LVDS output 1, compliant with the LVDS standard with an internal 100 Ω termination between OUT1+ and OUT1-."
},
{
"number": "27",
"name": "OUT1+",
"type": "output",
"description": "Non-inverting high-speed LVDS output 1, compliant with the LVDS standard with an internal 100 Ω termination between OUT1+ and OUT1-."
},
{
"number": "28",
"name": "OUT0-",
"type": "output",
"description": "Inverting high-speed LVDS output 0, compliant with the LVDS standard with an internal 100 Ω termination between OUT0+ and OUT0-."
},
{
"number": "29",
"name": "OUT0+",
"type": "output",
"description": "Non-inverting high-speed LVDS output 0, compliant with the LVDS standard with an internal 100 Ω termination between OUT0+ and OUT0-."
},
{
"number": "30",
"name": "VDD",
"type": "power_in",
"description": "Power supply pin; the device is specified for VCC of 3.0 V to 3.6 V (3.3 V typical)."
},
{
"number": "31",
"name": "PE0",
"type": "input",
"description": "LVCMOS transmit pre-emphasis level select for output OUT0; logic 0 sets pre-emphasis OFF and logic 1 sets it ON."
},
{
"number": "32",
"name": "PWDN3",
"type": "input",
"description": "LVCMOS channel power-down pin for output OUT3; when set low, output OUT3 is in power-down mode."
},
{
"number": "33",
"name": "PWDN2",
"type": "input",
"description": "LVCMOS channel power-down pin for output OUT2; when set low, output OUT2 is in power-down mode."
},
{
"number": "34",
"name": "PWDN1",
"type": "input",
"description": "LVCMOS channel power-down pin for output OUT1; when set low, output OUT1 is in power-down mode."
},
{
"number": "35",
"name": "PWDN0",
"type": "input",
"description": "LVCMOS channel power-down pin for output OUT0; when set low, output OUT0 is in power-down mode."
},
{
"number": "36",
"name": "LOS2",
"type": "output",
"description": "Open-drain loss-of-signal output for input IN2 that reports an open-input fault; an external pull-up resistor is required."
},
{
"number": "37",
"name": "LOS1",
"type": "output",
"description": "Open-drain loss-of-signal output for input IN1 that reports an open-input fault; an external pull-up resistor is required."
},
{
"number": "38",
"name": "PWDN",
"type": "input",
"description": "LVCMOS device power-down pin; when set low, the whole device is in power-down mode."
},
{
"number": "39",
"name": "EQ1",
"type": "input",
"description": "LVCMOS receive equalization level select for input IN1; logic 0 sets equalization OFF and logic 1 sets it ON."
},
{
"number": "40",
"name": "NC",
"type": "unconnected",
"description": "No-connect pin; may be left floating."
},
{
"number": "41",
"name": "EP",
"type": "passive",
"description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The page 2 pin diagram text is scrambled in extraction. The 40-pin mapping was rebuilt from the diag; The exposed die attach pad (DAP) is the GND thermal pad. It has no numbered pin, so it is not listed; Supply limits (3.0 V to 3.6 V) come from the page 4 Recommended Operating Conditions, not the page 3",
"exposed pad 41 added from the footprint"
],
"pages_sent": 20,
"cost_usd": 0.1045,
"at": "2026-10-11T07:26:16"
},
"datasheet": {
"url": "https://www.ti.com/cn/lit/gpn/ds25br204",
"pages": 20,
"sha256": "876ac681a1460722",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 41,
"described": 41,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
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"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
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"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "e5b4286c2329085d9ef7f90d5eb5bf41a435241ecc1baaf1383823b6d6a946ae",
"checked": "2026-10-11",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "ds25br204tsq-etched.step",
"role": "eda",
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"origin": "footprint origin = pad-pattern centre",
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"footprint_binding": "identity",
"sha256": "ecd8c9b332fc2e1e2c241a8cfaf342599251358788e148f667239cff6444088d",
"checked": "2026-10-11",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
},
"metadata": {
"specs": {
"Manufacturer": "Texas Instruments",
"Package": "WQFN-40(6x6)",
"Category": "Interface",
"Pins": "41"
}
},
"variants": [],
"sections": [
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"info"
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"discovery_triggers": [
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],
"discovery_pitch": "DS25BR204TSQ (Texas Instruments) component page: datasheet pinout, KiCad symbol, footprint and 3D.",
"author": {
"name": "Ray",
"email": "[email protected]"
},
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