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DS25BR204TSQ

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Texas Instruments LVDS ICs, WQFN-40(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

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DS25BR204TSQ

Texas Instruments · LVDS ICs · WQFN-40(6x6)

DS25BR204TSQ from Texas Instruments, in a WQFN-40(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No-connect pin; may be left floating.
2 NC unconnected No-connect pin; may be left floating.
3 VDD power_in Power supply pin; the device is specified for VCC of 3.0 V to 3.6 V (3.3 V typical).
4 IN1+ input Non-inverting high-speed LVDS input 1, internally terminated with 100 Ω between IN1+ and IN1-, accepting LVDS, CML and LVPECL levels.
5 IN1- input Inverting high-speed LVDS input 1, internally terminated with 100 Ω between IN1+ and IN1-.
6 IN2+ input Non-inverting high-speed LVDS input 2, internally terminated with 100 Ω between IN2+ and IN2-, accepting LVDS, CML and LVPECL levels.
7 IN2- input Inverting high-speed LVDS input 2, internally terminated with 100 Ω between IN2+ and IN2-.
8 VDD power_in Power supply pin; the device is specified for VCC of 3.0 V to 3.6 V (3.3 V typical).
9 NC unconnected No-connect pin; may be left floating.
10 NC unconnected No-connect pin; may be left floating.
11 EQ2 input LVCMOS receive equalization level select for input IN2; logic 0 sets equalization OFF and logic 1 sets it ON.
12 NC unconnected No-connect pin; may be left floating.
13 NC unconnected No-connect pin; may be left floating.
14 SEL_in input LVCMOS input select pin; logic 0 selects IN1 and logic 1 selects IN2.
15 VDD power_in Power supply pin; the device is specified for VCC of 3.0 V to 3.6 V (3.3 V typical).
16 GND power_in Ground pin; the device ground, which is also connected to the exposed die attach pad (DAP).
17 NC unconnected No-connect pin; may be left floating.
18 PE3 input LVCMOS transmit pre-emphasis level select for output OUT3; logic 0 sets pre-emphasis OFF and logic 1 sets it ON.
19 PE2 input LVCMOS transmit pre-emphasis level select for output OUT2; logic 0 sets pre-emphasis OFF and logic 1 sets it ON.
20 PE1 input LVCMOS transmit pre-emphasis level select for output OUT1; logic 0 sets pre-emphasis OFF and logic 1 sets it ON.
21 OUT3- output Inverting high-speed LVDS output 3, compliant with the LVDS standard with an internal 100 Ω termination between OUT3+ and OUT3-.
22 OUT3+ output Non-inverting high-speed LVDS output 3, compliant with the LVDS standard with an internal 100 Ω termination between OUT3+ and OUT3-.
23 OUT2- output Inverting high-speed LVDS output 2, compliant with the LVDS standard with an internal 100 Ω termination between OUT2+ and OUT2-.
24 OUT2+ output Non-inverting high-speed LVDS output 2, compliant with the LVDS standard with an internal 100 Ω termination between OUT2+ and OUT2-.
25 VDD power_in Power supply pin; the device is specified for VCC of 3.0 V to 3.6 V (3.3 V typical).
26 OUT1- output Inverting high-speed LVDS output 1, compliant with the LVDS standard with an internal 100 Ω termination between OUT1+ and OUT1-.
27 OUT1+ output Non-inverting high-speed LVDS output 1, compliant with the LVDS standard with an internal 100 Ω termination between OUT1+ and OUT1-.
28 OUT0- output Inverting high-speed LVDS output 0, compliant with the LVDS standard with an internal 100 Ω termination between OUT0+ and OUT0-.
29 OUT0+ output Non-inverting high-speed LVDS output 0, compliant with the LVDS standard with an internal 100 Ω termination between OUT0+ and OUT0-.
30 VDD power_in Power supply pin; the device is specified for VCC of 3.0 V to 3.6 V (3.3 V typical).
31 PE0 input LVCMOS transmit pre-emphasis level select for output OUT0; logic 0 sets pre-emphasis OFF and logic 1 sets it ON.
32 PWDN3 input LVCMOS channel power-down pin for output OUT3; when set low, output OUT3 is in power-down mode.
33 PWDN2 input LVCMOS channel power-down pin for output OUT2; when set low, output OUT2 is in power-down mode.
34 PWDN1 input LVCMOS channel power-down pin for output OUT1; when set low, output OUT1 is in power-down mode.
35 PWDN0 input LVCMOS channel power-down pin for output OUT0; when set low, output OUT0 is in power-down mode.
36 LOS2 output Open-drain loss-of-signal output for input IN2 that reports an open-input fault; an external pull-up resistor is required.
37 LOS1 output Open-drain loss-of-signal output for input IN1 that reports an open-input fault; an external pull-up resistor is required.
38 PWDN input LVCMOS device power-down pin; when set low, the whole device is in power-down mode.
39 EQ1 input LVCMOS receive equalization level select for input IN1; logic 0 sets equalization OFF and logic 1 sets it ON.
40 NC unconnected No-connect pin; may be left floating.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-40(6x6)
Category Interface
Pins 41

CAD (KiCad official)

  • Symbol: DS25BR204TSQ
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: WQFN-40(6x6) (KiCad packages3D, STEP)
  • 3D model files: ds25br204tsq-etched.step / ds25br204tsq-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds25br204tsq.step / ds25br204tsq.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (20 pp, sha256 876ac681a1460722, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF