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DS16EV5110ASQX

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Texas Instruments Video Interface ICs, WQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DS16EV5110ASQX

Texas Instruments · Video Interface ICs · WQFN-48-EP(7x7)

DS16EV5110ASQX from Texas Instruments, in a WQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 C_IN- input Inverting TMDS clock input (CML) to the equalizer, with an on-chip 50Ω termination resistor to VDD.
2 C_IN+ input Non-inverting TMDS clock input (CML) to the equalizer, with an on-chip 50Ω termination resistor to VDD.
3 VDD power_in Power supply pin (3.0V to 3.6V), tied to the VDD plane through a low inductance path with a 0.1µF bypass capacitor to GND.
4 D_IN0- input Inverting TMDS data 0 input (CML) to the equalizer, with an on-chip 50Ω termination resistor to VDD.
5 D_IN0+ input Non-inverting TMDS data 0 input (CML) to the equalizer, with an on-chip 50Ω termination resistor to VDD.
6 VDD power_in Power supply pin (3.0V to 3.6V), tied to the VDD plane through a low inductance path with a 0.1µF bypass capacitor to GND.
7 VDD power_in Power supply pin (3.0V to 3.6V), tied to the VDD plane through a low inductance path with a 0.1µF bypass capacitor to GND.
8 D_IN1- input Inverting TMDS data 1 input (CML) to the equalizer, with an on-chip 50Ω termination resistor to VDD.
9 D_IN1+ input Non-inverting TMDS data 1 input (CML) to the equalizer, with an on-chip 50Ω termination resistor to VDD.
10 VDD power_in Power supply pin (3.0V to 3.6V), tied to the VDD plane through a low inductance path with a 0.1µF bypass capacitor to GND.
11 D_IN2- input Inverting TMDS data 2 input (CML) to the equalizer, with an on-chip 50Ω termination resistor to VDD.
12 D_IN2+ input Non-inverting TMDS data 2 input (CML) to the equalizer, with an on-chip 50Ω termination resistor to VDD.
13 VDD power_in Power supply pin (3.0V to 3.6V), tied to the VDD plane through a low inductance path with a 0.1µF bypass capacitor to GND.
14 BST_1 input LVCMOS equalizer boost select bit 1 (with BST_0 and BST_2 selects 1 of 8 boost levels), internally pulled Low.
15 VDD power_in Power supply pin (3.0V to 3.6V), tied to the VDD plane through a low inductance path with a 0.1µF bypass capacitor to GND.
16 CS input SMBus chip select: High enables the equalizer SMBus register, Low disables it; internally pulled Low and gated with SDC.
17 SDC input SMBus clock input (LVCMOS), internally pulled High to 3.3V with a High-Z pull up.
18 SDA bidirectional SMBus data input/output (LVCMOS), internally pulled High to 3.3V with a High-Z pull up.
19 Reserv unconnected Reserved; do not connect.
20 Reserv unconnected Reserved; do not connect.
21 FEB input Force External Boost: High sets boost from the BST_[0:2] pins, Low sets boost through the SMBus; internally pulled High.
22 GND power_in Ground reference, tied to a solid ground plane through a low impedance path.
23 BST_0 input LVCMOS equalizer boost select bit 0 (with BST_1 and BST_2 selects 1 of 8 boost levels), internally pulled Low.
24 GND power_in Ground reference, tied to a solid ground plane through a low impedance path.
25 D_OUT2+ output Non-inverting TMDS data 2 output (CML) from the equalizer, open collector.
26 D_OUT2- output Inverting TMDS data 2 output (CML) from the equalizer, open collector.
27 GND power_in Ground reference, tied to a solid ground plane through a low impedance path.
28 D_OUT1+ output Non-inverting TMDS data 1 output (CML) from the equalizer, open collector.
29 D_OUT1- output Inverting TMDS data 1 output (CML) from the equalizer, open collector.
30 GND power_in Ground reference, tied to a solid ground plane through a low impedance path.
31 GND power_in Ground reference, tied to a solid ground plane through a low impedance path.
32 D_OUT0+ output Non-inverting TMDS data 0 output (CML) from the equalizer, open collector.
33 D_OUT0- output Inverting TMDS data 0 output (CML) from the equalizer, open collector.
34 GND power_in Ground reference, tied to a solid ground plane through a low impedance path.
35 C_OUT+ output Non-inverting TMDS clock output (CML) from the equalizer, open collector.
36 C_OUT- output Inverting TMDS clock output (CML) from the equalizer, open collector.
37 BST_2 input LVCMOS equalizer boost select bit 2 (with BST_0 and BST_1 selects 1 of 8 boost levels), internally pulled Low.
38 Reserv unconnected Reserved; do not connect.
39 Reserv unconnected Reserved; do not connect.
40 Reserv unconnected Reserved; do not connect.
41 Reserv unconnected Reserved; do not connect.
42 Reserv unconnected Reserved; do not connect.
43 Reserv unconnected Reserved; do not connect.
44 EN input Enable input: High selects normal operation, Low selects standby mode; internally pulled High and global to all data and clock channels.
45 SD output LVCMOS clock channel signal detect output, High when signal is detected.
46 VDD power_in Power supply pin (3.0V to 3.6V), tied to the VDD plane through a low inductance path with a 0.1µF bypass capacitor to GND.
47 Reserv unconnected Reserved; do not connect.
48 Reserv unconnected Reserved; do not connect.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-48-EP(7x7)
Category Communication Interface Chip/UART/485/232
Pins 49

CAD (KiCad official)

  • Symbol: DS16EV5110ASQX
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: WQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: ds16ev5110asqx-etched.step / ds16ev5110asqx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds16ev5110asqx.step / ds16ev5110asqx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (25 pp, sha256 8197f99e1a4a9be5, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF