component
DS16EV5110ASQX
Public Made by Adomby adom
Texas Instruments Video Interface ICs, WQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
README.mdadded+85@@ -0,0 +1,85 @@+# DS16EV5110ASQX++**Texas Instruments** · Video Interface ICs · WQFN-48-EP(7x7)++DS16EV5110ASQX from Texas Instruments, in a WQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | C_IN- | input | Inverting TMDS clock input (CML) to the equalizer, with an on-chip 50Ω termination resistor to VDD. |+| 2 | C_IN+ | input | Non-inverting TMDS clock input (CML) to the equalizer, with an on-chip 50Ω termination resistor to VDD. |+| 3 | VDD | power_in | Power supply pin (3.0V to 3.6V), tied to the VDD plane through a low inductance path with a 0.1µF bypass capacitor to GND. |+| 4 | D_IN0- | input | Inverting TMDS data 0 input (CML) to the equalizer, with an on-chip 50Ω termination resistor to VDD. |+| 5 | D_IN0+ | input | Non-inverting TMDS data 0 input (CML) to the equalizer, with an on-chip 50Ω termination resistor to VDD. |+| 6 | VDD | power_in | Power supply pin (3.0V to 3.6V), tied to the VDD plane through a low inductance path with a 0.1µF bypass capacitor to GND. |+| 7 | VDD | power_in | Power supply pin (3.0V to 3.6V), tied to the VDD plane through a low inductance path with a 0.1µF bypass capacitor to GND. |+| 8 | D_IN1- | input | Inverting TMDS data 1 input (CML) to the equalizer, with an on-chip 50Ω termination resistor to VDD. |+| 9 | D_IN1+ | input | Non-inverting TMDS data 1 input (CML) to the equalizer, with an on-chip 50Ω termination resistor to VDD. |+| 10 | VDD | power_in | Power supply pin (3.0V to 3.6V), tied to the VDD plane through a low inductance path with a 0.1µF bypass capacitor to GND. |+| 11 | D_IN2- | input | Inverting TMDS data 2 input (CML) to the equalizer, with an on-chip 50Ω termination resistor to VDD. |+| 12 | D_IN2+ | input | Non-inverting TMDS data 2 input (CML) to the equalizer, with an on-chip 50Ω termination resistor to VDD. |+| 13 | VDD | power_in | Power supply pin (3.0V to 3.6V), tied to the VDD plane through a low inductance path with a 0.1µF bypass capacitor to GND. |+| 14 | BST_1 | input | LVCMOS equalizer boost select bit 1 (with BST_0 and BST_2 selects 1 of 8 boost levels), internally pulled Low. |+| 15 | VDD | power_in | Power supply pin (3.0V to 3.6V), tied to the VDD plane through a low inductance path with a 0.1µF bypass capacitor to GND. |+| 16 | CS | input | SMBus chip select: High enables the equalizer SMBus register, Low disables it; internally pulled Low and gated with SDC. |+| 17 | SDC | input | SMBus clock input (LVCMOS), internally pulled High to 3.3V with a High-Z pull up. |+| 18 | SDA | bidirectional | SMBus data input/output (LVCMOS), internally pulled High to 3.3V with a High-Z pull up. |+| 19 | Reserv | unconnected | Reserved; do not connect. |+| 20 | Reserv | unconnected | Reserved; do not connect. |+| 21 | FEB | input | Force External Boost: High sets boost from the BST_[0:2] pins, Low sets boost through the SMBus; internally pulled High. |+| 22 | GND | power_in | Ground reference, tied to a solid ground plane through a low impedance path. |+| 23 | BST_0 | input | LVCMOS equalizer boost select bit 0 (with BST_1 and BST_2 selects 1 of 8 boost levels), internally pulled Low. |+| 24 | GND | power_in | Ground reference, tied to a solid ground plane through a low impedance path. |+| 25 | D_OUT2+ | output | Non-inverting TMDS data 2 output (CML) from the equalizer, open collector. |+| 26 | D_OUT2- | output | Inverting TMDS data 2 output (CML) from the equalizer, open collector. |+| 27 | GND | power_in | Ground reference, tied to a solid ground plane through a low impedance path. |+| 28 | D_OUT1+ | output | Non-inverting TMDS data 1 output (CML) from the equalizer, open collector. |+| 29 | D_OUT1- | output | Inverting TMDS data 1 output (CML) from the equalizer, open collector. |+| 30 | GND | power_in | Ground reference, tied to a solid ground plane through a low impedance path. |+| 31 | GND | power_in | Ground reference, tied to a solid ground plane through a low impedance path. |+| 32 | D_OUT0+ | output | Non-inverting TMDS data 0 output (CML) from the equalizer, open collector. |+| 33 | D_OUT0- | output | Inverting TMDS data 0 output (CML) from the equalizer, open collector. |+| 34 | GND | power_in | Ground reference, tied to a solid ground plane through a low impedance path. |+| 35 | C_OUT+ | output | Non-inverting TMDS clock output (CML) from the equalizer, open collector. |+| 36 | C_OUT- | output | Inverting TMDS clock output (CML) from the equalizer, open collector. |+| 37 | BST_2 | input | LVCMOS equalizer boost select bit 2 (with BST_0 and BST_1 selects 1 of 8 boost levels), internally pulled Low. |+| 38 | Reserv | unconnected | Reserved; do not connect. |+| 39 | Reserv | unconnected | Reserved; do not connect. |+| 40 | Reserv | unconnected | Reserved; do not connect. |+| 41 | Reserv | unconnected | Reserved; do not connect. |+| 42 | Reserv | unconnected | Reserved; do not connect. |+| 43 | Reserv | unconnected | Reserved; do not connect. |+| 44 | EN | input | Enable input: High selects normal operation, Low selects standby mode; internally pulled High and global to all data and clock channels. |+| 45 | SD | output | LVCMOS clock channel signal detect output, High when signal is detected. |+| 46 | VDD | power_in | Power supply pin (3.0V to 3.6V), tied to the VDD plane through a low inductance path with a 0.1µF bypass capacitor to GND. |+| 47 | Reserv | unconnected | Reserved; do not connect. |+| 48 | Reserv | unconnected | Reserved; do not connect. |+| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | WQFN-48-EP(7x7) |+| Category | Communication Interface Chip/UART/485/232 |+| Pins | 49 |++## CAD (KiCad official)++- Symbol: `DS16EV5110ASQX`+- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`+- 3D model: WQFN-48-EP(7x7) (KiCad packages3D, STEP)+- 3D model files: `ds16ev5110asqx-etched.step` / `ds16ev5110asqx-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ds16ev5110asqx.step` / `ds16ev5110asqx.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ds16ev5110a) (25 pp, sha256 `8197f99e1a4a9be5`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ds16ev5110asqx-datasheet.pdf)
page.jsonadded+444@@ -0,0 +1,444 @@+{+ "slug": "ds16ev5110asqx",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Video Interface ICs, WQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "communication interface chip-uart-485-232",+ "ds16ev5110asqx",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "ds16ev5110asqx.kicad_sym",+ "ds16ev5110asqx.kicad_mod",+ "ds16ev5110asqx.glb",+ "ds16ev5110asqx.step",+ "ds16ev5110asqx.lbr",+ "docs/hero.png",+ "docs/ds16ev5110asqx-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "ds16ev5110asqx-hero.glb",+ "ds16ev5110asqx-hero.overlay.json"+ ],+ "component": {+ "mpn": "DS16EV5110ASQX",+ "manufacturer": "Texas Instruments",+ "package": "WQFN-48-EP(7x7)",+ "pin_count": 49,+ "category": "Communication Interface Chip/UART/485/232",+ "subcategory": "Video Interface ICs",+ "datasheet": "https://www.ti.com/cn/lit/gpn/ds16ev5110a",+ "parts": {+ "symbol": "ds16ev5110asqx.kicad_sym",+ "footprint": "ds16ev5110asqx.kicad_mod",+ "model_3d": "ds16ev5110asqx-hero.glb",+ "model_3d_plain": "ds16ev5110asqx.glb",+ "model_3d_step": "ds16ev5110asqx-etched.step",+ "model_3d_step_plain": "ds16ev5110asqx.step",+ "lbr": "ds16ev5110asqx.lbr"+ },+ "distributor_links": {+ "lcsc": "C2927519"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T18:02:51Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": null,+ "status": "no match"+ },+ "mouser": {+ "pn": null,+ "status": "no match"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "C_IN-",+ "type": "input",+ "description": "Inverting TMDS clock input (CML) to the equalizer, with an on-chip 50Ω termination resistor to VDD."+ },+ {+ "number": "2",+ "name": "C_IN+",+ "type": "input",+ "description": "Non-inverting TMDS clock input (CML) to the equalizer, with an on-chip 50Ω termination resistor to VDD."+ },+ {+ "number": "3",+ "name": "VDD",+ "type": "power_in",+ "description": "Power supply pin (3.0V to 3.6V), tied to the VDD plane through a low inductance path with a 0.1µF bypass capacitor to GND."+ },+ {+ "number": "4",+ "name": "D_IN0-",+ "type": "input",+ "description": "Inverting TMDS data 0 input (CML) to the equalizer, with an on-chip 50Ω termination resistor to VDD."+ },+ {+ "number": "5",+ "name": "D_IN0+",+ "type": "input",+ "description": "Non-inverting TMDS data 0 input (CML) to the equalizer, with an on-chip 50Ω termination resistor to VDD."+ },+ {+ "number": "6",+ "name": "VDD",+ "type": "power_in",+ "description": "Power supply pin (3.0V to 3.6V), tied to the VDD plane through a low inductance path with a 0.1µF bypass capacitor to GND."+ },+ {+ "number": "7",+ "name": "VDD",+ "type": "power_in",+ "description": "Power supply pin (3.0V to 3.6V), tied to the VDD plane through a low inductance path with a 0.1µF bypass capacitor to GND."+ },+ {+ "number": "8",+ "name": "D_IN1-",+ "type": "input",+ "description": "Inverting TMDS data 1 input (CML) to the equalizer, with an on-chip 50Ω termination resistor to VDD."+ },+ {+ "number": "9",+ "name": "D_IN1+",+ "type": "input",+ "description": "Non-inverting TMDS data 1 input (CML) to the equalizer, with an on-chip 50Ω termination resistor to VDD."+ },+ {+ "number": "10",+ "name": "VDD",+ "type": "power_in",+ "description": "Power supply pin (3.0V to 3.6V), tied to the VDD plane through a low inductance path with a 0.1µF bypass capacitor to GND."+ },+ {+ "number": "11",+ "name": "D_IN2-",+ "type": "input",+ "description": "Inverting TMDS data 2 input (CML) to the equalizer, with an on-chip 50Ω termination resistor to VDD."+ },+ {+ "number": "12",+ "name": "D_IN2+",+ "type": "input",+ "description": "Non-inverting TMDS data 2 input (CML) to the equalizer, with an on-chip 50Ω termination resistor to VDD."+ },+ {+ "number": "13",+ "name": "VDD",+ "type": "power_in",+ "description": "Power supply pin (3.0V to 3.6V), tied to the VDD plane through a low inductance path with a 0.1µF bypass capacitor to GND."+ },+ {+ "number": "14",+ "name": "BST_1",+ "type": "input",+ "description": "LVCMOS equalizer boost select bit 1 (with BST_0 and BST_2 selects 1 of 8 boost levels), internally pulled Low."+ },+ {+ "number": "15",+ "name": "VDD",+ "type": "power_in",+ "description": "Power supply pin (3.0V to 3.6V), tied to the VDD plane through a low inductance path with a 0.1µF bypass capacitor to GND."+ },+ {+ "number": "16",+ "name": "CS",+ "type": "input",+ "description": "SMBus chip select: High enables the equalizer SMBus register, Low disables it; internally pulled Low and gated with SDC."+ },+ {+ "number": "17",+ "name": "SDC",+ "type": "input",+ "description": "SMBus clock input (LVCMOS), internally pulled High to 3.3V with a High-Z pull up."+ },+ {+ "number": "18",+ "name": "SDA",+ "type": "bidirectional",+ "description": "SMBus data input/output (LVCMOS), internally pulled High to 3.3V with a High-Z pull up."+ },+ {+ "number": "19",+ "name": "Reserv",+ "type": "unconnected",+ "description": "Reserved; do not connect."+ },+ {+ "number": "20",+ "name": "Reserv",+ "type": "unconnected",+ "description": "Reserved; do not connect."+ },+ {+ "number": "21",+ "name": "FEB",+ "type": "input",+ "description": "Force External Boost: High sets boost from the BST_[0:2] pins, Low sets boost through the SMBus; internally pulled High."+ },+ {+ "number": "22",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference, tied to a solid ground plane through a low impedance path."+ },+ {+ "number": "23",+ "name": "BST_0",+ "type": "input",+ "description": "LVCMOS equalizer boost select bit 0 (with BST_1 and BST_2 selects 1 of 8 boost levels), internally pulled Low."+ },+ {+ "number": "24",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference, tied to a solid ground plane through a low impedance path."+ },+ {+ "number": "25",+ "name": "D_OUT2+",+ "type": "output",+ "description": "Non-inverting TMDS data 2 output (CML) from the equalizer, open collector."+ },+ {+ "number": "26",+ "name": "D_OUT2-",+ "type": "output",+ "description": "Inverting TMDS data 2 output (CML) from the equalizer, open collector."+ },+ {+ "number": "27",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference, tied to a solid ground plane through a low impedance path."+ },+ {+ "number": "28",+ "name": "D_OUT1+",+ "type": "output",+ "description": "Non-inverting TMDS data 1 output (CML) from the equalizer, open collector."+ },+ {+ "number": "29",+ "name": "D_OUT1-",+ "type": "output",+ "description": "Inverting TMDS data 1 output (CML) from the equalizer, open collector."+ },+ {+ "number": "30",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference, tied to a solid ground plane through a low impedance path."+ },+ {+ "number": "31",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference, tied to a solid ground plane through a low impedance path."+ },+ {+ "number": "32",+ "name": "D_OUT0+",+ "type": "output",+ "description": "Non-inverting TMDS data 0 output (CML) from the equalizer, open collector."+ },+ {+ "number": "33",+ "name": "D_OUT0-",+ "type": "output",+ "description": "Inverting TMDS data 0 output (CML) from the equalizer, open collector."+ },+ {+ "number": "34",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference, tied to a solid ground plane through a low impedance path."+ },+ {+ "number": "35",+ "name": "C_OUT+",+ "type": "output",+ "description": "Non-inverting TMDS clock output (CML) from the equalizer, open collector."+ },+ {+ "number": "36",+ "name": "C_OUT-",+ "type": "output",+ "description": "Inverting TMDS clock output (CML) from the equalizer, open collector."+ },+ {+ "number": "37",+ "name": "BST_2",+ "type": "input",+ "description": "LVCMOS equalizer boost select bit 2 (with BST_0 and BST_1 selects 1 of 8 boost levels), internally pulled Low."+ },+ {+ "number": "38",+ "name": "Reserv",+ "type": "unconnected",+ "description": "Reserved; do not connect."+ },+ {+ "number": "39",+ "name": "Reserv",+ "type": "unconnected",+ "description": "Reserved; do not connect."+ },+ {+ "number": "40",+ "name": "Reserv",+ "type": "unconnected",+ "description": "Reserved; do not connect."+ },+ {+ "number": "41",+ "name": "Reserv",+ "type": "unconnected",+ "description": "Reserved; do not connect."+ },+ {+ "number": "42",+ "name": "Reserv",+ "type": "unconnected",+ "description": "Reserved; do not connect."+ },+ {+ "number": "43",+ "name": "Reserv",+ "type": "unconnected",+ "description": "Reserved; do not connect."+ },+ {+ "number": "44",+ "name": "EN",+ "type": "input",+ "description": "Enable input: High selects normal operation, Low selects standby mode; internally pulled High and global to all data and clock channels."+ },+ {+ "number": "45",+ "name": "SD",+ "type": "output",+ "description": "LVCMOS clock channel signal detect output, High when signal is detected."+ },+ {+ "number": "46",+ "name": "VDD",+ "type": "power_in",+ "description": "Power supply pin (3.0V to 3.6V), tied to the VDD plane through a low inductance path with a 0.1µF bypass capacitor to GND."+ },+ {+ "number": "47",+ "name": "Reserv",+ "type": "unconnected",+ "description": "Reserved; do not connect."+ },+ {+ "number": "48",+ "name": "Reserv",+ "type": "unconnected",+ "description": "Reserved; do not connect."+ },+ {+ "number": "49",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Package variant check: the datasheet gives the package as a 7 mm x 7 mm, 48-pin leadless WQFN (NJU),; Exposed pad: the center exposed pad (DAP) is GND and must be connected to the ground plane. It has n; Top-view drawing on page 3 is garbled in the text extraction. The pin-number-to-name mapping was tak",+ "exposed pad 49 added from the footprint"+ ],+ "pages_sent": 7,+ "cost_usd": 0.0861,+ "at": "2026-10-08T18:02:18"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/ds16ev5110a",+ "pages": 25,+ "sha256": "8197f99e1a4a9be5",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 49,+ "described": 49,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "ds16ev5110asqx.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7,+ 7,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "f2b38b0b4bf967c77e683e8d4599608b9f0503055ec535b93c4ebb5d0163e916",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "ds16ev5110asqx-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7,+ 7,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "5741c53d39d43b5eb16eb20d4e00584c040c5c25a05ae39c9b09f2bff5d844e1",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}