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DS15BR401TVSX

Texas Instruments · LVDS ICs · TQFP-48(7x7)

DS15BR401TVSX from Texas Instruments, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	N/C	unconnected	No connect pin on the TQFP package; leave unconnected.
2	PEM	input	LVTTL pre-emphasis control input that applies to all channels (0 = off, 1 = on, about 6 dB boost at 750 MHz); VIH is 2.0 V minimum and VIL is 0.8 V maximum.
3	VDD	power_in	3.3 V supply pin (VDD = 3.3 V ±10%, recommended 3.0 V to 3.6 V); decouple close to the pin.
4	VDD	power_in	3.3 V supply pin (VDD = 3.3 V ±10%, recommended 3.0 V to 3.6 V); decouple close to the pin.
5	VDD	power_in	3.3 V supply pin (VDD = 3.3 V ±10%, recommended 3.0 V to 3.6 V); decouple close to the pin.
6	N/C	unconnected	No connect pin on the TQFP package; leave unconnected.
7	VDD	power_in	3.3 V supply pin (VDD = 3.3 V ±10%, recommended 3.0 V to 3.6 V); decouple close to the pin.
8	GND	power_in	Ground reference for LVDS and CMOS circuitry.
9	GND	power_in	Ground reference for LVDS and CMOS circuitry.
10	VDD	power_in	3.3 V supply pin (VDD = 3.3 V ±10%, recommended 3.0 V to 3.6 V); decouple close to the pin.
11	VDD	power_in	3.3 V supply pin (VDD = 3.3 V ±10%, recommended 3.0 V to 3.6 V); decouple close to the pin.
12	PWDN	input	LVTTL input; a logic low activates the hardware power-down mode for all channels, powering off all input and output buffers and internal bias.
13	IN0+	input	Channel 0 non-inverting LVDS differential input (differential input voltage 100 mV to 2400 mV); the DS15BR400 has an internal 100 Ω termination across IN0+/IN0-.
14	IN0-	input	Channel 0 inverting LVDS differential input (differential input voltage 100 mV to 2400 mV); the DS15BR400 has an internal 100 Ω termination across IN0+/IN0-.
15	IN1+	input	Channel 1 non-inverting LVDS differential input (differential input voltage 100 mV to 2400 mV); the DS15BR400 has an internal 100 Ω termination across IN1+/IN1-.
16	IN1-	input	Channel 1 inverting LVDS differential input (differential input voltage 100 mV to 2400 mV); the DS15BR400 has an internal 100 Ω termination across IN1+/IN1-.
17	GND	power_in	Ground reference for LVDS and CMOS circuitry.
18	GND	power_in	Ground reference for LVDS and CMOS circuitry.
19	IN2+	input	Channel 2 non-inverting LVDS differential input (differential input voltage 100 mV to 2400 mV); the DS15BR400 has an internal 100 Ω termination across IN2+/IN2-.
20	IN2-	input	Channel 2 inverting LVDS differential input (differential input voltage 100 mV to 2400 mV); the DS15BR400 has an internal 100 Ω termination across IN2+/IN2-.
21	IN3+	input	Channel 3 non-inverting LVDS differential input (differential input voltage 100 mV to 2400 mV); the DS15BR400 has an internal 100 Ω termination across IN3+/IN3-.
22	IN3-	input	Channel 3 inverting LVDS differential input (differential input voltage 100 mV to 2400 mV); the DS15BR400 has an internal 100 Ω termination across IN3+/IN3-.
23	GND	power_in	Ground reference for LVDS and CMOS circuitry.
24	GND	power_in	Ground reference for LVDS and CMOS circuitry.
25	N/C	unconnected	No connect pin on the TQFP package; leave unconnected.
26	N/C	unconnected	No connect pin on the TQFP package; leave unconnected.
27	N/C	unconnected	No connect pin on the TQFP package; leave unconnected.
28	VDD	power_in	3.3 V supply pin (VDD = 3.3 V ±10%, recommended 3.0 V to 3.6 V); decouple close to the pin.
29	VDD	power_in	3.3 V supply pin (VDD = 3.3 V ±10%, recommended 3.0 V to 3.6 V); decouple close to the pin.
30	N/C	unconnected	No connect pin on the TQFP package; leave unconnected.
31	N/C	unconnected	No connect pin on the TQFP package; leave unconnected.
32	VDD	power_in	3.3 V supply pin (VDD = 3.3 V ±10%, recommended 3.0 V to 3.6 V); decouple close to the pin.
33	VDD	power_in	3.3 V supply pin (VDD = 3.3 V ±10%, recommended 3.0 V to 3.6 V); decouple close to the pin.
34	N/C	unconnected	No connect pin on the TQFP package; leave unconnected.
35	N/C	unconnected	No connect pin on the TQFP package; leave unconnected.
36	N/C	unconnected	No connect pin on the TQFP package; leave unconnected.
37	GND	power_in	Ground reference for LVDS and CMOS circuitry.
38	GND	power_in	Ground reference for LVDS and CMOS circuitry.
39	OUT3-	output	Channel 3 inverting LVDS differential output with 100 Ω integrated output termination; for point-to-point backplane and cable use only, not multidrop (BLVDS).
40	OUT3+	output	Channel 3 non-inverting LVDS differential output with 100 Ω integrated output termination; for point-to-point backplane and cable use only, not multidrop (BLVDS).
41	OUT2-	output	Channel 2 inverting LVDS differential output with 100 Ω integrated output termination; for point-to-point backplane and cable use only, not multidrop (BLVDS).
42	OUT2+	output	Channel 2 non-inverting LVDS differential output with 100 Ω integrated output termination; for point-to-point backplane and cable use only, not multidrop (BLVDS).
43	GND	power_in	Ground reference for LVDS and CMOS circuitry.
44	GND	power_in	Ground reference for LVDS and CMOS circuitry.
45	OUT1-	output	Channel 1 inverting LVDS differential output with 100 Ω integrated output termination; for point-to-point backplane and cable use only, not multidrop (BLVDS).
46	OUT1+	output	Channel 1 non-inverting LVDS differential output with 100 Ω integrated output termination; for point-to-point backplane and cable use only, not multidrop (BLVDS).
47	OUT0-	output	Channel 0 inverting LVDS differential output with 100 Ω integrated output termination; for point-to-point backplane and cable use only, not multidrop (BLVDS).
48	OUT0+	output	Channel 0 non-inverting LVDS differential output with 100 Ω integrated output termination; for point-to-point backplane and cable use only, not multidrop (BLVDS).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TQFP-48(7x7)
Category	Interface
Pins	48

CAD (KiCad official)

Symbol: DS15BR401TVSX
Footprint: Package_QFP:TQFP-48_7x7mm_P0.5mm
3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
3D model files: ds15br401tvsx-etched.step / ds15br401tvsx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds15br401tvsx.step / ds15br401tvsx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (24 pp, sha256 d2f51d86ec9c5b5f, retrieved 2026-10-08, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF