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DRV8889AQWRGERQ1

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Texas Instruments Stepper Motor Driver, VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DRV8889AQWRGERQ1

Texas Instruments · Stepper Motor Driver · VQFN-24-EP(4x4)

DRV8889AQWRGERQ1 from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VM power_in Motor supply pin with an operating range of 4.5 V to 45 V and an absolute maximum of 50 V; bypass with a 0.01 µF ceramic rated for VM placed close to the pin and a bulk capacitor rated for VM.
2 PGND power_in Power ground; both PGND pins are internally shorted and must be connected to the system ground on the PCB.
3 AOUT1 output Winding A output connected to the stepper motor; continuous phase-node voltage is limited to -1.0 V to VM + 1.0 V (100 ns transient -3.0 V to VM + 3.0 V).
4 AOUT2 output Winding A output connected to the stepper motor; continuous phase-node voltage is limited to -1.0 V to VM + 1.0 V (100 ns transient -3.0 V to VM + 3.0 V).
5 BOUT2 output Winding B output connected to the stepper motor; continuous phase-node voltage is limited to -1.0 V to VM + 1.0 V (100 ns transient -3.0 V to VM + 3.0 V).
6 BOUT1 output Winding B output connected to the stepper motor; continuous phase-node voltage is limited to -1.0 V to VM + 1.0 V (100 ns transient -3.0 V to VM + 3.0 V).
7 PGND power_in Power ground; both PGND pins are internally shorted and must be connected to the system ground on the PCB.
8 VM power_in Motor supply pin with an operating range of 4.5 V to 45 V and an absolute maximum of 50 V; bypass with a 0.01 µF ceramic rated for VM placed close to the pin and a bulk capacitor rated for VM.
9 GND power_in Device ground; connect to the system ground.
10 DVDD power_out Logic supply from the internal regulator (nominal 5 V, supplies up to 2 mA); bypass to GND with a 0.47 µF, 6.3 V or 10 V X7R ceramic capacitor placed close to the pin.
11 nFAULT output Open-drain fault indication output that is pulled low on a fault and requires an external pull-up to 5 V or 3.3 V; absolute maximum sink current is 10 mA.
12 VREF power_in Current-setting reference input with a maximum of 3.3 V; DVDD can be divided down through a resistor divider to supply VREF.
13 nSCS input Active-low serial chip select for SPI communication; internal pull-up to DVDD.
14 VSDO power_in Supply pin for the SDO output, to be connected to 5 V or 3.3 V depending on the required logic level; SDO buffer supply range is 2.9 V to 5.5 V.
15 SDO output Push-pull SPI serial data output that shifts data out on the rising edge of SCLK.
16 SDI input Serial data input for SPI that is captured on the falling edge of SCLK.
17 SCLK input Serial clock input; serial data is shifted out and captured on the corresponding rising and falling edges of this pin.
18 STEP input Step input in which each rising edge advances the indexer by one step; internal pull-down resistor.
19 DIR input Direction input whose logic level sets the step direction; internal pull-down resistor.
20 DRVOFF input Logic high disables the device outputs and logic low enables them; internal pull-up to DVDD.
21 nSLEEP input Sleep-mode input where logic high enables the device and logic low enters low-power sleep; internal pull-down resistor, and it must not be tied to DVDD or the device cannot exit sleep.
22 CPL passive Charge-pump negative switching node; connect a 0.022 µF X7R ceramic capacitor rated for VM between CPH and CPL, with an absolute maximum of -0.3 V to VM.
23 CPH passive Charge-pump switching node; connect a 0.022 µF X7R ceramic capacitor rated for VM between CPH and CPL, with an absolute maximum of -0.3 V to VM + 7 V.
24 VCP power_out Charge-pump output; connect a 0.22 µF 16 V X7R ceramic capacitor between VCP and VM.
25 PAD passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-24-EP(4x4)
Category Motor Driver ICs
Pins 25

CAD (KiCad official)

  • Symbol: DRV8889AQWRGERQ1
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm
  • 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: drv8889aqwrgerq1-etched.step / drv8889aqwrgerq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); drv8889aqwrgerq1.step / drv8889aqwrgerq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (87 pp, sha256 133d373031764255, retrieved 2026-10-07, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF