component
DRV8714SQRVJRQ1
Public Made by Adomby adom
Texas Instruments Gate Drivers, VQFN-56(8x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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DRV8714SQRVJRQ1
Texas Instruments · Gate Drivers · VQFN-56(8x8)
DRV8714SQRVJRQ1 from Texas Instruments, in a VQFN-56(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SCLK | input | Serial clock input; SPI data is shifted out and captured on the corresponding rising and falling edges of this pin, with an internal pull-down. |
| 2 | SDI | input | Serial data input, captured on the falling edge of SCLK, with an internal pull-down. |
| 3 | SDO | output | Serial data output, shifted out on the rising edge of SCLK; push-pull output referenced to the DVDD input. |
| 4 | IN1/EN1 | input | Half-bridge and H-bridge control input (IN1 or EN1 depending on mode, see section 7.3.3), with an internal pull-down. |
| 5 | IN2/PH1 | input | Half-bridge and H-bridge control input (IN2 or PH1 depending on mode, see section 7.3.3), with an internal pull-down. |
| 6 | IN3/EN2 | input | Half-bridge and H-bridge control input (IN3 or EN2 depending on mode, see section 7.3.3), with an internal pull-down. |
| 7 | IN4/PH2 | input | Half-bridge and H-bridge control input (IN4 or PH2 depending on mode, see section 7.3.3), with an internal pull-down. |
| 8 | nSLEEP | input | Device enable pin; driving it to logic low shuts the device down into sleep mode, with an internal pull-down. |
| 9 | DRVOFF/nFLT | bidirectional | Multi-function pin: DRVOFF global gate driver disable input (logic high disables the drivers) or nFLT open-drain fault indicator output that requires an external pull-up; internal pull-down. |
| 10 | AREF | power_in | External voltage reference and supply for the current shunt amplifiers; a 0.1 µF, 6.3 V ceramic capacitor to AGND is recommended, with AREF specified at 3 V to 5.5 V. |
| 11 | AGND | power_in | Device ground for the shunt amplifier section; connect to system ground. |
| 12 | SO1 | output | Current shunt amplifier 1 output, clamped to the AREF voltage to protect the controller ADC input. |
| 13 | SO2 | output | Current shunt amplifier 2 output, clamped to the AREF voltage to protect the controller ADC input. |
| 14 | BRAKE | input | Power-off braking pin; driving it high during low-power sleep mode enables the low-side gate drivers, with an internal pull-down, and it must be tied to GND if the feature is unused. |
| 15 | SP1 | input | Shunt amplifier 1 non-inverting input; connect to the positive terminal of the shunt resistor. |
| 16 | SN1 | input | Shunt amplifier 1 inverting input; connect to the negative terminal of the shunt resistor. |
| 17 | SP2 | input | Shunt amplifier 2 non-inverting input; connect to the positive terminal of the shunt resistor. |
| 18 | SN2 | input | Shunt amplifier 2 inverting input; connect to the negative terminal of the shunt resistor. |
| 19 | NC | unconnected | No connection on the DRV8714S-Q1 (this position is GL1 on the DRV8718S-Q1); leave unconnected. |
| 20 | NC | unconnected | No connection on the DRV8714S-Q1 (this position is SH1 on the DRV8718S-Q1); leave unconnected. |
| 21 | NC | unconnected | No connection on the DRV8714S-Q1 (this position is GH1 on the DRV8718S-Q1); leave unconnected. |
| 22 | GH1 | output | High-side gate driver output for half-bridge 1; connects to the gate of the high-side MOSFET. |
| 23 | SH1 | input | High-side source sense input for half-bridge 1; connects to the high-side MOSFET source. |
| 24 | GL1 | output | Low-side gate driver output for half-bridge 1; connects to the gate of the low-side MOSFET. |
| 25 | PGND1 | power_in | Low-side MOSFET gate driver 1-4 sense and power return; connect to system ground close to the device and half-bridges 1-4. |
| 26 | GL2 | output | Low-side gate driver output for half-bridge 2; connects to the gate of the low-side MOSFET. |
| 27 | SH2 | input | High-side source sense input for half-bridge 2; connects to the high-side MOSFET source. |
| 28 | GH2 | output | High-side gate driver output for half-bridge 2; connects to the gate of the high-side MOSFET. |
| 29 | NC | unconnected | No connection on the DRV8714S-Q1 (this position is GH4 on the DRV8718S-Q1); leave unconnected. |
| 30 | NC | unconnected | No connection on the DRV8714S-Q1 (this position is SH4 on the DRV8718S-Q1); leave unconnected. |
| 31 | NC | unconnected | No connection on the DRV8714S-Q1 (this position is GL4 on the DRV8718S-Q1); leave unconnected. |
| 32 | GND | power_in | Device ground; connect to system ground. |
| 33 | CP2L | bidirectional | Charge pump 2 switching node; connect a 100 nF ceramic capacitor rated for PVDD between CP2H and CP2L. |
| 34 | CP2H | bidirectional | Charge pump 2 switching node; connect a 100 nF ceramic capacitor rated for PVDD between CP2H and CP2L. |
| 35 | CP1L | bidirectional | Charge pump 1 switching node; connect a 100 nF ceramic capacitor rated for PVDD between CP1H and CP1L. |
| 36 | CP1H | bidirectional | Charge pump 1 switching node; connect a 100 nF ceramic capacitor rated for PVDD between CP1H and CP1L. |
| 37 | VCP | bidirectional | Charge pump output; connect a 1 µF, 16 V ceramic capacitor between VCP and PVDD. |
| 38 | PVDD | power_in | Gate driver supply input connected to the bridge supply; requires a 0.1 µF PVDD-rated ceramic capacitor and at least 10 µF bulk capacitance to GND, with a recommended operating range of 4.9 V to 37 V (40 V absolute maximum). |
| 39 | DRAIN | input | Bridge MOSFET drain voltage sense pin; connect to the common point of the high-side MOSFET drains. |
| 40 | NC | unconnected | No connection. |
| 41 | NC | unconnected | No connection on the DRV8714S-Q1 (this position is GL5 on the DRV8718S-Q1); leave unconnected. |
| 42 | NC | unconnected | No connection on the DRV8714S-Q1 (this position is SH5 on the DRV8718S-Q1); leave unconnected. |
| 43 | NC | unconnected | No connection on the DRV8714S-Q1 (this position is GH5 on the DRV8718S-Q1); leave unconnected. |
| 44 | GH3 | output | High-side gate driver output for half-bridge 3; connects to the gate of the high-side MOSFET. |
| 45 | SH3 | input | High-side source sense input for half-bridge 3; connects to the high-side MOSFET source. |
| 46 | GL3 | output | Low-side gate driver output for half-bridge 3; connects to the gate of the low-side MOSFET. |
| 47 | PGND2 | power_in | Low-side MOSFET gate driver sense and power return for the second group of gate drivers (listed as 5-8 in the RVJ table); connect to system ground close to the device and half-bridges. |
| 48 | GL4 | output | Low-side gate driver output for half-bridge 4; connects to the gate of the low-side MOSFET. |
| 49 | SH4 | input | High-side source sense input for half-bridge 4; connects to the high-side MOSFET source. |
| 50 | GH4 | output | High-side gate driver output for half-bridge 4; connects to the gate of the high-side MOSFET. |
| 51 | NC | unconnected | No connection on the DRV8714S-Q1 (this position is GH8 on the DRV8718S-Q1); leave unconnected. |
| 52 | NC | unconnected | No connection on the DRV8714S-Q1 (this position is SH8 on the DRV8718S-Q1); leave unconnected. |
| 53 | NC | unconnected | No connection on the DRV8714S-Q1 (this position is GL8 on the DRV8718S-Q1); leave unconnected. |
| 54 | DGND | power_in | Device ground for the digital logic; connect to system ground. |
| 55 | DVDD | power_in | Device logic and digital output supply input, operating from 3 V to 5.5 V; connect a 1.0 µF, 6.3 V ceramic capacitor between DVDD and GND. |
| 56 | nSCS | input | Serial chip select; logic low enables SPI communication, with an internal pull-up. |
| 57 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-56(8x8) |
| Category | Motor Driver ICs |
| Pins | 57 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Driver supply voltage PVDD | VPVDD | 4.9 | 37 | V | 在工作温度范围内（除非另有说明） | 23 | |
| High-side average gate drive current GHx | IHS | 0 | 15 | mA | 在工作温度范围内（除非另有说明） | 23 | |
| Low-side average gate drive current GLx | ILS | 0 | 15 | mA | 在工作温度范围内（除非另有说明） | 23 | |
| Digital supply voltage DVDD | VDVDD | 3 | 5.5 | V | 在工作温度范围内（除非另有说明） | 23 | |
| Digital input voltage (BRAKE, DRVOFF/nFLT, INx/ENx, INx/PHx, nSLEEP, nSCS, SCLK, SDI) | VDIN | 0 | 5.5 | V | 在工作温度范围内（除非另有说明） | 23 | |
| Digital output current SDO | IDOUT | 0 | 5 | mA | 在工作温度范围内（除非另有说明） | 23 | |
| Open-drain pull-up voltage DRVOFF/nFLT | VOD | 0 | 5.5 | V | 在工作温度范围内（除非另有说明） | 23 | |
| Open-drain output current DRVOFF/nFLT | IOD | 0 | 5 | mA | 在工作温度范围内（除非另有说明） | 23 | |
| Brake input voltage BRAKE | VBRAKE | 0 | V | 在工作温度范围内（除非另有说明）；printed maximum is PVDD | 23 | ||
| Amplifier reference supply voltage AREF | VAREF | 3 | 5.5 | V | 在工作温度范围内（除非另有说明） | 23 | |
| Shunt amplifier output current SOx | ISO | 0 | 5 | mA | 在工作温度范围内（除非另有说明） | 23 | |
| Operating ambient temperature | TA | -40 | 125 | °C | 23 | ||
| Operating junction temperature | TJ | -40 | 150 | °C | 23 | ||
| PVDD sleep current (BRAKE = 0V) | IPVDDQ | 2.25 | 3.5 | µA | VPVDD、VDRAIN = 13.5V，nSLEEP = 0V，BRAKE = 0V，-40 ≤ TJ ≤ 85°C | 24 | |
| PVDD sleep current (BRAKE = 5V) | IPVDDQ | 10 | 15 | µA | VPVDD、VDRAIN = 13.5V，nSLEEP = 0V，BRAKE = 5V，-40 ≤ TJ ≤ 85°C | 24 | |
| DRAIN sleep current | IDRAINQ | 1.25 | 2 | µA | VPVDD，VDRAIN = 13.5V，nSLEEP = 0V，-40 ≤ TJ ≤ 85°C | 24 | |
| DVDD sleep current | IDVDDQ | 1.25 | 3 | µA | VPVDD，VDRAIN = 13.5V，nSLEEP = 0V，-40 ≤ TJ ≤ 85°C | 24 | |
| PVDD active mode current | IPVDD | 13.5 | 15.5 | mA | VPVDD，VDRAIN = 13.5V，nSLEEP = 5V | 24 | |
| DRAIN active mode current | IDRAIN | 1 | 1.65 | mA | VPVDD、VDRAIN = 13.5V，nSLEEP = 5V，VDS_LVL ≤ 500mV | 24 | |
| DVDD active mode current | IDVDD | 8 | 10 | mA | VDVDD = 5V，SDO = 0V | 24 | |
| Charge pump regulator voltage relative to PVDD, triple mode | VVCP | 9.5 | 10.5 | 11 | V | 三倍频模式，VPVDD ≥ 9V，IVCP ≤ 30mA | 24 |
| Charge pump regulator voltage relative to PVDD, triple mode | VVCP | 8.5 | 9 | 11 | V | 三倍频模式，VPVDD = 7V，IVCP ≤ 25mA | 24 |
| Charge pump regulator voltage relative to PVDD, triple mode | VVCP | 7 | 7.5 | 11 | V | 三倍频模式，VPVDD = 4.9V，IVCP ≤ 12mA | 24 |
| Charge pump regulator voltage relative to PVDD, doubling mode | VVCP | 9.5 | 10.5 | 11 | V | 二倍频模式，VPVDD ≥ 13V，IVCP ≤ 25mA | 24 |
| Charge pump regulator voltage relative to PVDD, doubling mode | VVCP | 7 | 8 | 11 | V | 二倍频模式，VPVDD = 9V，IVCP ≤ 13.5mA | 24 |
| Charge pump regulator voltage relative to PVDD, doubling mode | VVCP | 5.4 | 6 | 11 | V | 二倍频模式，VPVDD = 7V，IVCP ≤ 10mA | 24 |
| Input logic low voltage (DRVOFF/nFLT, INx/ENx, INx/PHx, nSLEEP, SCLK, SDI) | VIL | 0 | V | 24 | |||
| Input logic low voltage BRAKE | VIL | 0 | 0.6 | V | BRAKE | 24 | |
| Input logic high voltage (DRVOFF/nFLT, INx/ENx, INx/PHx, nSLEEP, SCLK, SDI) | VIH | 5.5 | V | 24 | |||
| Input logic high voltage BRAKE | VIH | 1.8 | 5.5 | V | BRAKE | 24 | |
| Input logic low current | IIL | -5 | 5 | µA | VDIN = 0V，BRAKE、DRVOFF/nFLT、INx/ENx、INx/PHx、nSLEEP、SCLK、SDI | 25 | |
| Input logic low current nSCS | IIL | 50 | 100 | µA | VDIN = 0V，nSCS | 25 | |
| Input logic high current | IIH | 50 | 100 | µA | VDIN = 5V，DRVOFF/nFLT、INx/ENx、INx/PHx、nSLEEP、SCLK、SDI | 25 | |
| Input logic high current BRAKE (nSLEEP = 0V) | IIH | 5 | 10 | µA | VDIN = 5V，nSLEEP = 0V，BRAKE | 25 | |
| Input logic high current BRAKE (nSLEEP = 5V) | IIH | 35 | 100 | µA | VDIN = 5V，nSLEEP = 5V，BRAKE | 25 | |
| Input logic high current nSCS | IIH | -5 | 5 | µA | VDIN = 5V，VDVDD = 5V，nSCS | 25 | |
| Input pull-down resistance | RPD | 50 | 100 | 150 | kΩ | 至 GND：DRVOFF/nFLT、INx/ENx、INx/PHx、nSLEEP、SCLK、SDI | 25 |
| BRAKE pull-down resistance (nSLEEP = 0V) | RPD | 500 | 1000 | 1500 | kΩ | BRAKE 至 GND，nSLEEP = 0V，BRAKE ≤ 2 V，4.9V ≤ VPVDD ≤ VPOB_OV | 25 |
| BRAKE pull-down resistance (nSLEEP = 5V) | RPD | 50 | 136 | 200 | kΩ | BRAKE 至 GND，nSLEEP = 5V，BRAKE ≤ 2 V，4.9V ≤ VPVDD ≤ VPOB_OV | 25 |
| Input pull-up resistance nSCS | RPU | 50 | 100 | 150 | kΩ | 至 DVDD，nSCS | 25 |
| Four-level input 1 voltage (GAIN, MODE) | VQI1 | 0 | V | 通过电压设置为电平 1 | 25 | ||
| Four-level input 2 resistance to GND (GAIN, MODE) | RQI2 | 44.65 | 47 | 49.35 | kΩ | 通过连接至 GND 的电阻设置为电平 2 | 25 |
| Four-level input 4 voltage (GAIN, MODE) | VQI4 | 5.5 | V | 电压连接至所设置的电平 4 | 25 | ||
| Six-level input 2 resistance to GND (IDRIVE, VDS) | RSI2 | 28.5 | 30 | 31.5 | kΩ | GND 电阻连接至所设置的电平 2 | 25 |
| Six-level input 3 resistance to GND (IDRIVE, VDS) | RSI3 | 95 | 100 | 105 | kΩ | GND 电阻连接至所设置的电平 3 | 25 |
| Six-level input 5 resistance to DVDD (IDRIVE, VDS) | RSI5 | 58.9 | 62 | 65.1 | kΩ | DVDD 电阻连接至所设置的电平 5 | 25 |
| Six-level input 1 voltage (IDRIVE, VDS) | VSI1 | 0 | V | 电压连接至所设置的电平 1 | 25 | ||
| Six-level input 6 voltage (IDRIVE, VDS) | RSI6 | 5.5 | V | 电压连接至所设置的电平 6 | 25 | ||
| Output logic low voltage (DRVOFF/nFLT, SDO) | VOL | 0.5 | V | IDOUT = 5mA | 25 | ||
| Junction-to-ambient thermal resistance (VQFN 56-pin RVJ, DRV8714-Q1 column) | RθJA | 24.7 | °C/W | 23 | |||
| Junction-to-case (top) thermal resistance (VQFN 56-pin RVJ, DRV8714-Q1 column) | RθJC(top) | 14.1 | °C/W | 23 | |||
| Junction-to-board thermal resistance (VQFN 56-pin RVJ, DRV8714-Q1 column) | RθJB | 9 | °C/W | 23 | |||
| Junction-to-top characterization parameter (VQFN 56-pin RVJ, DRV8714-Q1 column) | ΨJT | 0.2 | °C/W | 23 | |||
| Junction-to-board characterization parameter (VQFN 56-pin RVJ, DRV8714-Q1 column) | ΨJB | 9 | °C/W | 23 | |||
| Junction-to-case (bottom) thermal resistance (VQFN 56-pin RVJ, DRV8714-Q1 column) | RθJC(bot) | 2.3 | °C/W | 23 |
CAD (KiCad official)
- Symbol:
DRV8714SQRVJRQ1 - Footprint:
Package_DFN_QFN:QFN-56-1EP_8x8mm_P0.5mm_EP4.5x5.2mm - 3D model: VQFN-56(8x8) (KiCad packages3D, STEP)
- 3D model files:
drv8714sqrvjrq1-etched.step/drv8714sqrvjrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);drv8714sqrvjrq1.step/drv8714sqrvjrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (193 pp, sha256
a2520e0a5afb2156, retrieved 2026-10-19, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# DRV8714SQRVJRQ1
**Texas Instruments** · Gate Drivers · VQFN-56(8x8)
DRV8714SQRVJRQ1 from Texas Instruments, in a VQFN-56(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SCLK | input | Serial clock input; SPI data is shifted out and captured on the corresponding rising and falling edges of this pin, with an internal pull-down. |
| 2 | SDI | input | Serial data input, captured on the falling edge of SCLK, with an internal pull-down. |
| 3 | SDO | output | Serial data output, shifted out on the rising edge of SCLK; push-pull output referenced to the DVDD input. |
| 4 | IN1/EN1 | input | Half-bridge and H-bridge control input (IN1 or EN1 depending on mode, see section 7.3.3), with an internal pull-down. |
| 5 | IN2/PH1 | input | Half-bridge and H-bridge control input (IN2 or PH1 depending on mode, see section 7.3.3), with an internal pull-down. |
| 6 | IN3/EN2 | input | Half-bridge and H-bridge control input (IN3 or EN2 depending on mode, see section 7.3.3), with an internal pull-down. |
| 7 | IN4/PH2 | input | Half-bridge and H-bridge control input (IN4 or PH2 depending on mode, see section 7.3.3), with an internal pull-down. |
| 8 | nSLEEP | input | Device enable pin; driving it to logic low shuts the device down into sleep mode, with an internal pull-down. |
| 9 | DRVOFF/nFLT | bidirectional | Multi-function pin: DRVOFF global gate driver disable input (logic high disables the drivers) or nFLT open-drain fault indicator output that requires an external pull-up; internal pull-down. |
| 10 | AREF | power_in | External voltage reference and supply for the current shunt amplifiers; a 0.1 µF, 6.3 V ceramic capacitor to AGND is recommended, with AREF specified at 3 V to 5.5 V. |
| 11 | AGND | power_in | Device ground for the shunt amplifier section; connect to system ground. |
| 12 | SO1 | output | Current shunt amplifier 1 output, clamped to the AREF voltage to protect the controller ADC input. |
| 13 | SO2 | output | Current shunt amplifier 2 output, clamped to the AREF voltage to protect the controller ADC input. |
| 14 | BRAKE | input | Power-off braking pin; driving it high during low-power sleep mode enables the low-side gate drivers, with an internal pull-down, and it must be tied to GND if the feature is unused. |
| 15 | SP1 | input | Shunt amplifier 1 non-inverting input; connect to the positive terminal of the shunt resistor. |
| 16 | SN1 | input | Shunt amplifier 1 inverting input; connect to the negative terminal of the shunt resistor. |
| 17 | SP2 | input | Shunt amplifier 2 non-inverting input; connect to the positive terminal of the shunt resistor. |
| 18 | SN2 | input | Shunt amplifier 2 inverting input; connect to the negative terminal of the shunt resistor. |
| 19 | NC | unconnected | No connection on the DRV8714S-Q1 (this position is GL1 on the DRV8718S-Q1); leave unconnected. |
| 20 | NC | unconnected | No connection on the DRV8714S-Q1 (this position is SH1 on the DRV8718S-Q1); leave unconnected. |
| 21 | NC | unconnected | No connection on the DRV8714S-Q1 (this position is GH1 on the DRV8718S-Q1); leave unconnected. |
| 22 | GH1 | output | High-side gate driver output for half-bridge 1; connects to the gate of the high-side MOSFET. |
| 23 | SH1 | input | High-side source sense input for half-bridge 1; connects to the high-side MOSFET source. |
| 24 | GL1 | output | Low-side gate driver output for half-bridge 1; connects to the gate of the low-side MOSFET. |
| 25 | PGND1 | power_in | Low-side MOSFET gate driver 1-4 sense and power return; connect to system ground close to the device and half-bridges 1-4. |
| 26 | GL2 | output | Low-side gate driver output for half-bridge 2; connects to the gate of the low-side MOSFET. |
| 27 | SH2 | input | High-side source sense input for half-bridge 2; connects to the high-side MOSFET source. |
| 28 | GH2 | output | High-side gate driver output for half-bridge 2; connects to the gate of the high-side MOSFET. |
| 29 | NC | unconnected | No connection on the DRV8714S-Q1 (this position is GH4 on the DRV8718S-Q1); leave unconnected. |
| 30 | NC | unconnected | No connection on the DRV8714S-Q1 (this position is SH4 on the DRV8718S-Q1); leave unconnected. |
| 31 | NC | unconnected | No connection on the DRV8714S-Q1 (this position is GL4 on the DRV8718S-Q1); leave unconnected. |
| 32 | GND | power_in | Device ground; connect to system ground. |
| 33 | CP2L | bidirectional | Charge pump 2 switching node; connect a 100 nF ceramic capacitor rated for PVDD between CP2H and CP2L. |
| 34 | CP2H | bidirectional | Charge pump 2 switching node; connect a 100 nF ceramic capacitor rated for PVDD between CP2H and CP2L. |
| 35 | CP1L | bidirectional | Charge pump 1 switching node; connect a 100 nF ceramic capacitor rated for PVDD between CP1H and CP1L. |
| 36 | CP1H | bidirectional | Charge pump 1 switching node; connect a 100 nF ceramic capacitor rated for PVDD between CP1H and CP1L. |
| 37 | VCP | bidirectional | Charge pump output; connect a 1 µF, 16 V ceramic capacitor between VCP and PVDD. |
| 38 | PVDD | power_in | Gate driver supply input connected to the bridge supply; requires a 0.1 µF PVDD-rated ceramic capacitor and at least 10 µF bulk capacitance to GND, with a recommended operating range of 4.9 V to 37 V (40 V absolute maximum). |
| 39 | DRAIN | input | Bridge MOSFET drain voltage sense pin; connect to the common point of the high-side MOSFET drains. |
| 40 | NC | unconnected | No connection. |
| 41 | NC | unconnected | No connection on the DRV8714S-Q1 (this position is GL5 on the DRV8718S-Q1); leave unconnected. |
| 42 | NC | unconnected | No connection on the DRV8714S-Q1 (this position is SH5 on the DRV8718S-Q1); leave unconnected. |
| 43 | NC | unconnected | No connection on the DRV8714S-Q1 (this position is GH5 on the DRV8718S-Q1); leave unconnected. |
| 44 | GH3 | output | High-side gate driver output for half-bridge 3; connects to the gate of the high-side MOSFET. |
| 45 | SH3 | input | High-side source sense input for half-bridge 3; connects to the high-side MOSFET source. |
| 46 | GL3 | output | Low-side gate driver output for half-bridge 3; connects to the gate of the low-side MOSFET. |
| 47 | PGND2 | power_in | Low-side MOSFET gate driver sense and power return for the second group of gate drivers (listed as 5-8 in the RVJ table); connect to system ground close to the device and half-bridges. |
| 48 | GL4 | output | Low-side gate driver output for half-bridge 4; connects to the gate of the low-side MOSFET. |
| 49 | SH4 | input | High-side source sense input for half-bridge 4; connects to the high-side MOSFET source. |
| 50 | GH4 | output | High-side gate driver output for half-bridge 4; connects to the gate of the high-side MOSFET. |
| 51 | NC | unconnected | No connection on the DRV8714S-Q1 (this position is GH8 on the DRV8718S-Q1); leave unconnected. |
| 52 | NC | unconnected | No connection on the DRV8714S-Q1 (this position is SH8 on the DRV8718S-Q1); leave unconnected. |
| 53 | NC | unconnected | No connection on the DRV8714S-Q1 (this position is GL8 on the DRV8718S-Q1); leave unconnected. |
| 54 | DGND | power_in | Device ground for the digital logic; connect to system ground. |
| 55 | DVDD | power_in | Device logic and digital output supply input, operating from 3 V to 5.5 V; connect a 1.0 µF, 6.3 V ceramic capacitor between DVDD and GND. |
| 56 | nSCS | input | Serial chip select; logic low enables SPI communication, with an internal pull-up. |
| 57 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-56(8x8) |
| Category | Motor Driver ICs |
| Pins | 57 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Driver supply voltage PVDD | VPVDD | 4.9 | | 37 | V | 在工作温度范围内（除非另有说明） | 23 |
| High-side average gate drive current GHx | IHS | 0 | | 15 | mA | 在工作温度范围内（除非另有说明） | 23 |
| Low-side average gate drive current GLx | ILS | 0 | | 15 | mA | 在工作温度范围内（除非另有说明） | 23 |
| Digital supply voltage DVDD | VDVDD | 3 | | 5.5 | V | 在工作温度范围内（除非另有说明） | 23 |
| Digital input voltage (BRAKE, DRVOFF/nFLT, INx/ENx, INx/PHx, nSLEEP, nSCS, SCLK, SDI) | VDIN | 0 | | 5.5 | V | 在工作温度范围内（除非另有说明） | 23 |
| Digital output current SDO | IDOUT | 0 | | 5 | mA | 在工作温度范围内（除非另有说明） | 23 |
| Open-drain pull-up voltage DRVOFF/nFLT | VOD | 0 | | 5.5 | V | 在工作温度范围内（除非另有说明） | 23 |
| Open-drain output current DRVOFF/nFLT | IOD | 0 | | 5 | mA | 在工作温度范围内（除非另有说明） | 23 |
| Brake input voltage BRAKE | VBRAKE | 0 | | | V | 在工作温度范围内（除非另有说明）；printed maximum is PVDD | 23 |
| Amplifier reference supply voltage AREF | VAREF | 3 | | 5.5 | V | 在工作温度范围内（除非另有说明） | 23 |
| Shunt amplifier output current SOx | ISO | 0 | | 5 | mA | 在工作温度范围内（除非另有说明） | 23 |
| Operating ambient temperature | TA | -40 | | 125 | °C | | 23 |
| Operating junction temperature | TJ | -40 | | 150 | °C | | 23 |
| PVDD sleep current (BRAKE = 0V) | IPVDDQ | | 2.25 | 3.5 | µA | VPVDD、VDRAIN = 13.5V，nSLEEP = 0V，BRAKE = 0V，-40 ≤ TJ ≤ 85°C | 24 |
| PVDD sleep current (BRAKE = 5V) | IPVDDQ | | 10 | 15 | µA | VPVDD、VDRAIN = 13.5V，nSLEEP = 0V，BRAKE = 5V，-40 ≤ TJ ≤ 85°C | 24 |
| DRAIN sleep current | IDRAINQ | | 1.25 | 2 | µA | VPVDD，VDRAIN = 13.5V，nSLEEP = 0V，-40 ≤ TJ ≤ 85°C | 24 |
| DVDD sleep current | IDVDDQ | | 1.25 | 3 | µA | VPVDD，VDRAIN = 13.5V，nSLEEP = 0V，-40 ≤ TJ ≤ 85°C | 24 |
| PVDD active mode current | IPVDD | | 13.5 | 15.5 | mA | VPVDD，VDRAIN = 13.5V，nSLEEP = 5V | 24 |
| DRAIN active mode current | IDRAIN | | 1 | 1.65 | mA | VPVDD、VDRAIN = 13.5V，nSLEEP = 5V，VDS_LVL ≤ 500mV | 24 |
| DVDD active mode current | IDVDD | | 8 | 10 | mA | VDVDD = 5V，SDO = 0V | 24 |
| Charge pump regulator voltage relative to PVDD, triple mode | VVCP | 9.5 | 10.5 | 11 | V | 三倍频模式，VPVDD ≥ 9V，IVCP ≤ 30mA | 24 |
| Charge pump regulator voltage relative to PVDD, triple mode | VVCP | 8.5 | 9 | 11 | V | 三倍频模式，VPVDD = 7V，IVCP ≤ 25mA | 24 |
| Charge pump regulator voltage relative to PVDD, triple mode | VVCP | 7 | 7.5 | 11 | V | 三倍频模式，VPVDD = 4.9V，IVCP ≤ 12mA | 24 |
| Charge pump regulator voltage relative to PVDD, doubling mode | VVCP | 9.5 | 10.5 | 11 | V | 二倍频模式，VPVDD ≥ 13V，IVCP ≤ 25mA | 24 |
| Charge pump regulator voltage relative to PVDD, doubling mode | VVCP | 7 | 8 | 11 | V | 二倍频模式，VPVDD = 9V，IVCP ≤ 13.5mA | 24 |
| Charge pump regulator voltage relative to PVDD, doubling mode | VVCP | 5.4 | 6 | 11 | V | 二倍频模式，VPVDD = 7V，IVCP ≤ 10mA | 24 |
| Input logic low voltage (DRVOFF/nFLT, INx/ENx, INx/PHx, nSLEEP, SCLK, SDI) | VIL | 0 | | | V | | 24 |
| Input logic low voltage BRAKE | VIL | 0 | | 0.6 | V | BRAKE | 24 |
| Input logic high voltage (DRVOFF/nFLT, INx/ENx, INx/PHx, nSLEEP, SCLK, SDI) | VIH | | | 5.5 | V | | 24 |
| Input logic high voltage BRAKE | VIH | 1.8 | | 5.5 | V | BRAKE | 24 |
| Input logic low current | IIL | -5 | | 5 | µA | VDIN = 0V，BRAKE、DRVOFF/nFLT、INx/ENx、INx/PHx、nSLEEP、SCLK、SDI | 25 |
| Input logic low current nSCS | IIL | | 50 | 100 | µA | VDIN = 0V，nSCS | 25 |
| Input logic high current | IIH | | 50 | 100 | µA | VDIN = 5V，DRVOFF/nFLT、INx/ENx、INx/PHx、nSLEEP、SCLK、SDI | 25 |
| Input logic high current BRAKE (nSLEEP = 0V) | IIH | | 5 | 10 | µA | VDIN = 5V，nSLEEP = 0V，BRAKE | 25 |
| Input logic high current BRAKE (nSLEEP = 5V) | IIH | | 35 | 100 | µA | VDIN = 5V，nSLEEP = 5V，BRAKE | 25 |
| Input logic high current nSCS | IIH | -5 | | 5 | µA | VDIN = 5V，VDVDD = 5V，nSCS | 25 |
| Input pull-down resistance | RPD | 50 | 100 | 150 | kΩ | 至 GND：DRVOFF/nFLT、INx/ENx、INx/PHx、nSLEEP、SCLK、SDI | 25 |
| BRAKE pull-down resistance (nSLEEP = 0V) | RPD | 500 | 1000 | 1500 | kΩ | BRAKE 至 GND，nSLEEP = 0V，BRAKE ≤ 2 V，4.9V ≤ VPVDD ≤ VPOB_OV | 25 |
| BRAKE pull-down resistance (nSLEEP = 5V) | RPD | 50 | 136 | 200 | kΩ | BRAKE 至 GND，nSLEEP = 5V，BRAKE ≤ 2 V，4.9V ≤ VPVDD ≤ VPOB_OV | 25 |
| Input pull-up resistance nSCS | RPU | 50 | 100 | 150 | kΩ | 至 DVDD，nSCS | 25 |
| Four-level input 1 voltage (GAIN, MODE) | VQI1 | 0 | | | V | 通过电压设置为电平 1 | 25 |
| Four-level input 2 resistance to GND (GAIN, MODE) | RQI2 | 44.65 | 47 | 49.35 | kΩ | 通过连接至 GND 的电阻设置为电平 2 | 25 |
| Four-level input 4 voltage (GAIN, MODE) | VQI4 | | | 5.5 | V | 电压连接至所设置的电平 4 | 25 |
| Six-level input 2 resistance to GND (IDRIVE, VDS) | RSI2 | 28.5 | 30 | 31.5 | kΩ | GND 电阻连接至所设置的电平 2 | 25 |
| Six-level input 3 resistance to GND (IDRIVE, VDS) | RSI3 | 95 | 100 | 105 | kΩ | GND 电阻连接至所设置的电平 3 | 25 |
| Six-level input 5 resistance to DVDD (IDRIVE, VDS) | RSI5 | 58.9 | 62 | 65.1 | kΩ | DVDD 电阻连接至所设置的电平 5 | 25 |
| Six-level input 1 voltage (IDRIVE, VDS) | VSI1 | 0 | | | V | 电压连接至所设置的电平 1 | 25 |
| Six-level input 6 voltage (IDRIVE, VDS) | RSI6 | | | 5.5 | V | 电压连接至所设置的电平 6 | 25 |
| Output logic low voltage (DRVOFF/nFLT, SDO) | VOL | | | 0.5 | V | IDOUT = 5mA | 25 |
| Junction-to-ambient thermal resistance (VQFN 56-pin RVJ, DRV8714-Q1 column) | RθJA | | 24.7 | | °C/W | | 23 |
| Junction-to-case (top) thermal resistance (VQFN 56-pin RVJ, DRV8714-Q1 column) | RθJC(top) | | 14.1 | | °C/W | | 23 |
| Junction-to-board thermal resistance (VQFN 56-pin RVJ, DRV8714-Q1 column) | RθJB | | 9 | | °C/W | | 23 |
| Junction-to-top characterization parameter (VQFN 56-pin RVJ, DRV8714-Q1 column) | ΨJT | | 0.2 | | °C/W | | 23 |
| Junction-to-board characterization parameter (VQFN 56-pin RVJ, DRV8714-Q1 column) | ΨJB | | 9 | | °C/W | | 23 |
| Junction-to-case (bottom) thermal resistance (VQFN 56-pin RVJ, DRV8714-Q1 column) | RθJC(bot) | | 2.3 | | °C/W | | 23 |
## CAD (KiCad official)
- Symbol: `DRV8714SQRVJRQ1`
- Footprint: `Package_DFN_QFN:QFN-56-1EP_8x8mm_P0.5mm_EP4.5x5.2mm`
- 3D model: VQFN-56(8x8) (KiCad packages3D, STEP)
- 3D model files: `drv8714sqrvjrq1-etched.step` / `drv8714sqrvjrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `drv8714sqrvjrq1.step` / `drv8714sqrvjrq1.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/drv8714-q1) (193 pp, sha256 `a2520e0a5afb2156`, retrieved 2026-10-19, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/drv8714sqrvjrq1-datasheet.pdf)