component

DRV8353HMRTAT

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Texas Instruments Motor Driver ICs, WQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower supply chipdrv8353hmrtatfactory-2.0.0extractor-text

Verified DRV8353HMRTAT

by Ray · last 12 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

12 Nov 2026RayPublished by the parts factory: tier mfr, 41 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: DRV8353HMRTAT · WQFN-40-EP(6x6) · 41 pins
  • ✓copper: 41 copper pads, none touching another net
  • ✓datasheet: all 41 pin names found in the 73-page datasheet
  • ✓distributor: lcsc C2876350, digikey 296-DRV8353HMRTATTR-ND, mouser 595-DRV8353HMRTAT
  • ✓family: QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-136mg77i/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.70)
  • ✓pads: 41 pins = 41 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 41 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 52 kB, viewers/symbol.html 28 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ drv8353hmrtat.kicad_sym✓ drv8353hmrtat.kicad_mod✓ drv8353hmrtat.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers drv8353hmrtat: viewers rendered from the public page · Ray
drv8353hmrtat-etched.glb drv8353hmrtat: factory component page (tier=mfr) · Ray
drv8353hmrtat-etched.step drv8353hmrtat: factory component page (tier=mfr) · Ray
drv8353hmrtat-hero.glb drv8353hmrtat: hero GLB from the etched model (keeps the MPN mark) · Ray
drv8353hmrtat-hero.overlay.json drv8353hmrtat: hero GLB from the etched model (keeps the MPN mark) · Ray
drv8353hmrtat.glb Publish 0.1.0 · Ray
drv8353hmrtat.kicad_mod Publish 0.1.0 · Ray
drv8353hmrtat.kicad_sym Publish 0.1.0 · Ray
drv8353hmrtat.lbr Publish 0.1.0 · Ray
drv8353hmrtat.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier mfr, 41 pins · Ray

DRV8353HMRTAT

Texas Instruments · Motor Driver ICs · WQFN-40-EP(6x6)

DRV8353HMRTAT from Texas Instruments, in a WQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CPL passive Charge pump switching node; connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL pins.
2 CPH passive Charge pump switching node; connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL pins.
3 VM power_in Gate driver power supply input; connect to either VDRAIN or a separate gate driver supply, with a X5R or X7R, 0.1-µF, VM-rated ceramic and at least 10 µF of local capacitance between VM and GND.
4 VDRAIN input High-side MOSFET drain sense input and charge pump reference; connect to the common point of the MOSFET drains.
5 VCP power_out Charge pump output; connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VDRAIN pins.
6 GHA output High-side gate driver output; connect to the gate of the high-side power MOSFET.
7 SHA input High-side source sense input; connect to the high-side power MOSFET source.
8 GLA output Low-side gate driver output; connect to the gate of the low-side power MOSFET.
9 SPA input Low-side source sense and shunt amplifier input; connect to the low-side power MOSFET source and high-side of the current shunt resistor.
10 SNA input Shunt amplifier input; connect to the low-side of the current shunt resistor.
11 SNB input Shunt amplifier input; connect to the low-side of the current shunt resistor.
12 SPB input Low-side source sense and shunt amplifier input; connect to the low-side power MOSFET source and high-side of the current shunt resistor.
13 GLB output Low-side gate driver output; connect to the gate of the low-side power MOSFET.
14 SHB input High-side source sense input; connect to the high-side power MOSFET source.
15 GHB output High-side gate driver output; connect to the gate of the high-side power MOSFET.
16 GHC output High-side gate driver output; connect to the gate of the high-side power MOSFET.
17 SHC input High-side source sense input; connect to the high-side power MOSFET source.
18 GLC output Low-side gate driver output; connect to the gate of the low-side power MOSFET.
19 SPC input Low-side source sense and shunt amplifier input; connect to the low-side power MOSFET source and high-side of the current shunt resistor.
20 SNC input Shunt amplifier input; connect to the low-side of the current shunt resistor.
21 SOC output Shunt amplifier output.
22 SOB output Shunt amplifier output.
23 SOA output Shunt amplifier output.
24 VREF power_in Shunt amplifier power supply input and reference; connect a X5R or X7R, 0.1-µF, 6.3-V ceramic capacitor between the VREF and AGND pins.
25 AGND power_in Device analog ground; connect to system ground.
26 nFAULT output Fault indicator output (open-drain); pulled logic low during a fault condition and requires an external pullup resistor.
27 MODE input PWM input mode setting; a 4-level input pin set by an external resistor (DRV8353HM only).
28 IDRIVE input Gate drive output current setting; a 7-level input pin set by an external resistor (DRV8353HM only).
29 VDS input VDS monitor trip point setting; a 7-level input pin set by an external resistor (DRV8353HM only).
30 GAIN input Amplifier gain setting; a 4-level input pin set by an external resistor (DRV8353HM only).
31 ENABLE input Gate driver enable; a logic low puts the device into low power sleep mode, and an 8 to 40-µs low pulse can be used to reset fault conditions.
32 INHA input High-side gate driver control input; controls the output of the high-side gate driver.
33 INLA input Low-side gate driver control input; controls the output of the low-side gate driver.
34 INHB input High-side gate driver control input; controls the output of the high-side gate driver.
35 INLB input Low-side gate driver control input; controls the output of the low-side gate driver.
36 INHC input High-side gate driver control input; controls the output of the high-side gate driver.
37 INLC input Low-side gate driver control input; controls the output of the low-side gate driver.
38 DVDD power_out 5-V internal regulator output; connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and GND pins; this regulator can source up to 10 mA externally.
39 GND power_in Device power ground; connect to system ground.
40 VGLS power_out 11-V internal regulator output; connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VGLS and GND pins.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-40-EP(6x6)
Category Power Supply Chip
Pins 41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power supply pin voltage (VM) -0.3 80 V 5
Voltage differential between ground pins (AGND, BGND, DGND, PGND) -0.3 0.3 V 5
MOSFET drain sense pin voltage (VDRAIN) -0.3 102 V 5
MOSFET drain sense pin voltage slew rate (VDRAIN) 0 2 V/µs 5
Charge pump pin voltage (CPH, VCP) -0.3 V 5
Charge-pump negative-switching pin voltage (CPL) -0.3 V 5
Low-side gate drive regulator pin voltage (VGLS) -0.3 18 V 5
Internal logic regulator pin voltage (DVDD) -0.3 5.75 V 5
Digital pin voltage (ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nFAULT, nSCS, SCLK, SDI, SDO, VDS) -0.3 5.75 V 5
Continuous high-side gate drive pin voltage (GHx) -5 V 5
Transient 200-ns high-side gate drive pin voltage (GHx) -10 V 5
High-side gate drive pin voltage with respect to SHx (GHx) -0.3 16 V 5
Continuous high-side source sense pin voltage (SHx) -5 102 V 5
Continuous high-side source sense pin voltage (SHx), VDRAIN-referenced limit -5 V 5
Transient 200-ns high-side source sense pin voltage (SHx) -10 V 5
Continuous low-side gate drive pin voltage (GLx) -1 V 5
Transient 200-ns low-side gate drive pin voltage (GLx) -5 V 5
Continuous low-side source sense pin voltage (SLx) -1 1 V 5
Transient 200-ns low-side source sense pin voltage (SLx) -5 5 V 5
Continuous shunt amplifier input pin voltage (SNx, SPx) -1 1 V 5
Transient 200-ns shunt amplifier input pin voltage (SNx, SPx) -5 5 V 5
Reference input pin voltage (VREF) -0.3 5.75 V 5
Shunt amplifier output pin voltage (SOx) -0.3 V 5
Ambient temperature, TA TA -55 125 °C 5
Junction temperature, TJ TJ -55 150 °C 5
Gate driver power supply voltage (VM) VVM 9 75 V 7
Charge pump reference and drain voltage sense (VDRAIN) VVDRAIN 7 100 V 7
Input voltage (ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nSCS, SCLK, SDI, VDS) VI 0 5.5 V 7
Applied PWM signal (INHx, INLx) fPWM 0 200 kHz 7
Switch-node slew rate range (SHx) tSH 0 2 V/ns 7
High-side average gate-drive current (GHx) IGATE_HS 0 25 mA 7
Low-side average gate-drive current (GLx) IGATE_LS 0 25 mA 7
External load current (DVDD) IDVDD 0 10 mA 7
Reference voltage input (VREF) VVREF 3 5.5 V 7
Shunt amplifier output current (SOx) ISO 0 5 mA 7
Open drain pullup voltage (nFAULT, SDO) VOD 0 5.5 V 7
Open drain output current (nFAULT, SDO) IOD 0 5 mA 7
Operating ambient temperature TA -55 125 °C 7
Operating junction temperature TJ -55 150 °C 7
VM operating supply current IVM 8.5 13 mA VVM = VVDRAIN = 48 V, ENABLE = 3.3 V, INHx/INLx = 0 V 9
VDRAIN operating supply current IVDRAIN 1.9 4 mA VVM = VVDRAIN = 48 V, ENABLE = 3.3 V, INHx/INLx = 0 V 9
Sleep mode supply current ISLEEP 20 40 µA ENABLE = 0 V, VVM = VVDRAIN = 48 V, TA = 25°C 9
Sleep mode supply current ISLEEP 100 µA ENABLE = 0 V, VVM = VVDRAIN = 48 V, TA = 125°C 9
Reset pulse time tRST 5 40 us ENABLE = 0 V period to reset faults 9
DVDD regulator voltage VDVDD 4.75 5 5.25 V IDVDD = 0 to 10 mA 9
VCP operating voltage with respect to VDRAIN VVCP 9 10.5 12 V VVM = 15 V, IVCP = 0 to 25 mA 9
VCP operating voltage with respect to VDRAIN VVCP 7.5 10 11.5 V VVM = 12 V, IVCP = 0 to 20 mA 9
VCP operating voltage with respect to VDRAIN VVCP 6 8 9.5 V VVM = 10 V, IVCP = 0 to 15 mA 9
VCP operating voltage with respect to VDRAIN VVCP 5.5 7.5 8.5 V VVM = 9 V, IVCP = 0 to 10 mA 9
VGLS operating voltage with respect to GND VVGLS 13 14.5 16 V VVM = 15 V, IVGLS = 0 to 25 mA 9
VGLS operating voltage with respect to GND VVGLS 10 11.5 12.5 V VVM = 12 V, IVGLS = 0 to 20 mA 9
VGLS operating voltage with respect to GND VVGLS 8 9.5 10.5 V VVM = 10 V, IVGLS = 0 to 15 mA 9
VGLS operating voltage with respect to GND VVGLS 7 8.5 9.5 V VVM = 9 V, IVGLS = 0 to 10 mA 9
Input logic low voltage VIL 0 0.8 V 9
Input logic high voltage VIH 1.5 5.5 V 9
Input logic low current IIL -5 5 µA VVIN = 0 V 9
Input logic high current IIH 50 70 µA VVIN = 5 V 9
Propagation delay INHx/INLx transition to GHx/GLx transition tPD 200 ns 9
Output logic low voltage VOL 0.125 V IO = 5 mA 10
Output high impedance leakage IOZ -2 2 µA VO = 5 V 10

CAD (KiCad official)

  • Symbol: DRV8353HMRTAT
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: WQFN-40-EP(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.8 mm tall, datasheet A, max). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions come from the datasheet drawing where it was read and are defaults otherwise (see provenance.model_3d_generated), not the manufacturer's CAD (STEP)
  • 3D model files: drv8353hmrtat-etched.step / drv8353hmrtat-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); drv8353hmrtat.step / drv8353hmrtat.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (73 pp, sha256 b5927be7d0ce94a9, retrieved 2026-11-12, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF